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w78e516d/w78e058d data sheet 8-bit microcontroller publication release date: feb 15, 2011 - 1 - revision a09 table of contents- 1 general des cription ......................................................................................................... 4 2 features ....................................................................................................................... .......... 5 3 parts inform ation list ..................................................................................................... 6 3.1 lead free (rohs) parts information li st......................................................................... 6 4 pin config urations............................................................................................................. 7 5 pin descri ptions ............................................................................................................... ... 9 6 block diagram .................................................................................................................. .. 10 7 functional d escription.................................................................................................. 11 7.1 on-chip fl ash eprom ................................................................................................ 11 7.2 i/o ports...................................................................................................................... .. 11 7.3 serial i/o ..................................................................................................................... .. 11 7.4 timers ........................................................................................................................... 11 7.4.1 clock .......................................................................................................................... .... 12 7.5 interrupts..................................................................................................................... .. 12 7.6 data po inters ................................................................................................................ 12 7.7 architecture................................................................................................................... 12 7.7.1 alu ............................................................................................................................ .... 12 7.7.2 accumula tor ................................................................................................................... 12 7.7.3 b regi ster..................................................................................................................... .. 12 7.7.4 program stat us word ..................................................................................................... 12 7.7.5 stack po inter .................................................................................................................. 13 7.7.6 scratch-pa d ram ........................................................................................................... 13 7.7.7 aux-ram....................................................................................................................... 13 8 memory orga nization...................................................................................................... 14 8.1 program memory (o n-chip flash) ................................................................................. 14 8.2 scratch-pad ram and register map ............................................................................ 14 8.2.1 working r egister s .......................................................................................................... 16 8.2.2 bit addressabl e locat ions .............................................................................................. 16 8.2.3 stack .......................................................................................................................... .... 16 8.2.4 aux-ram....................................................................................................................... 16 9 special function registers ......................................................................................... 17 9.1 sfr detail bit descriptions .......................................................................................... 19 10 instruction.................................................................................................................... ...... 37 11 instructio n timi ng ............................................................................................................ 45 12 power mana gement.......................................................................................................... 46 12.1 idle mode ...................................................................................................................... 46 12.2 power down mode ....................................................................................................... 46 13 reset cond itions............................................................................................................... 47
w78e516d/w78e058d data sheet - 2 - 13.1 sources of reset............................................................................................................ 47 13.1.1 external reset .............................................................................................................. 47 13.1.2 watchdog time r reset................................................................................................. 47 13.1.3 software reset ............................................................................................................. 47 13.1.4 reset state ............................................................................................................. 47 13.2 interrupt sources .......................................................................................................... 48 13.3 priority level structure ................................................................................................. 48 13.4 interrupt response time .............................................................................................. 50 13.5 interrupt inputs.............................................................................................................. 50 14 programmable time rs/counters ............................................................................... 52 14.1 timer/counter s 0 & 1.................................................................................................... 52 14.2 time-base se lection..................................................................................................... 52 14.2.1 mode 0 ......................................................................................................................... 52 14.2.2 mode 1 ......................................................................................................................... 52 14.2.3 mode 2 ......................................................................................................................... 53 14.2.4 mode 3 ......................................................................................................................... 54 14.3 timer/count er 2 ............................................................................................................ 54 14.3.1 capture mode............................................................................................................... 54 14.3.2 auto-reload mode, counti ng up .................................................................................. 55 14.3.3 baud rate gener ator mode ......................................................................................... 56 15 watchdog timer................................................................................................................. 57 16 serial port .................................................................................................................... ...... 59 16.1 mode 0 ........................................................................................................................ 59 16.2 mode 1 ........................................................................................................................ 60 16.3 mode 2 ........................................................................................................................ 61 17 f04kboot mode (boot from 4k bytes of ldrom )................................................... 65 18 isp(in-system programming) ......................................................................................... 67 19 config bits .................................................................................................................... ....... 70 20 typical application cir cuits ........................................................................................ 72 21 electrical cha racteristics......................................................................................... 73 21.1 absolute maxi mum ratings .......................................................................................... 73 21.2 d.c. electrical characteristics .................................................................... 74 21.3 ac charact eristics.............................................................................................. 75 21.4 timing wa veforms ....................................................................................................... 77 21.4.1 program fetch cycle.................................................................................................... 77 21.4.2 data read cycle .......................................................................................................... 78 21.4.3 data writ e cycle........................................................................................................... 78 21.4.4 port acce ss cycle ........................................................................................................ 79 21.4.5 reset pin ac cess cycle ............................................................................................... 79 22 package dime nsio ns ......................................................................................................... 80 22.1 40-pin dip ..................................................................................................................... 80 22.2 44-pin plcc ................................................................................................................. 81 22.3 44-pin pqfp ................................................................................................................. 82
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 3 - revision a09 22.4 48-pin lqfp.................................................................................................................. 83 23 revision histor y ............................................................................................................... . 89
w78e516d/w78e058d data sheet - 4 - 1 general description the w78e516d/w78e058d series is an 8-bit microcontroller which has an in-system programmable flash eprom for on-chip firmware updating. the instruction sets of the w78e516d/w78e058d ar e fully compatible with the standard 8052. the w78e516d/w78e058d series contains a 64k/32k by tes of main flash eprom and a 4k bytes of auxiliary flash eprom which allows the contents of the 64k/32k bytes main flash eprom to be up- dated by the loader program located in the 4k bytes flash eprom; a 256 bytes of sram; 256 bytes of auxram; four 8-bit bi-directional and bit-addressable i/o ports; an additional 4-bit port p4; three 16-bit timer/counters; a serial port. these peripher als are supported by an 8 sources 2-level interrupt capability. to facilitate programming and ve rification, the flash eprom inside the w78e516d/w78e058d series allows the program me mory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. the w78e516d/w78e058d series microcontroller ha s two power reduction modes, idle mode and power-down mode, both of which are software selectabl e. the idle mode turns off the processor clock but allows for continued peripheral operation. th e power-down mode stops the crystal oscillator for minimum power consumption. the external clock ca n be stopped at any time and in any state without affecting the processor.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 5 - revision a09 2 features ? fully static design 8-bit cmos microcontroller ? optional 12t or 6t mode ? 12t mode, 12 clocks per machine cycle operation (default), speed up to 40 mhz/5v ? 6t mode, 6 clocks per machine cycle operati on set by the writer, speed up to 20 mhz/5v ? wide supply voltage of 2.4 to 5.5v ? temperature grade is (-40 o c~85 o c) ? 64k/32k bytes of in-system programmable fl ash eprom for application program (aprom) ? 4k bytes of auxiliary flash eprom for loader program (ldrom) ? low standby current at full supply voltage ? 512 bytes of on-chip ram. (include 256 by tes of aux-ram, software selectable) ? 64k bytes program memory address space and 64k bytes data memory address space ? one 4-bit multipurpose programmable port, additional int2 / int3 ? support watch dog timer ? three 16-bit timer/counters ? one full duplex serial port ? 8-sources, 2-level interrupt capability ? software reset ? built-in power management with idle mode and power down mode ? code protection ? packages: - lead free (rohs) dip 40: W78E516DDG - lead free (rohs) plcc 44: w78e516dpg - lead free (rohs) pqfp 44: w78e516dfg - lead free (rohs) lqfp 48: w78e516dlg - lead free (rohs) dip 40: w78e058ddg - lead free (rohs) plcc 44: w78e058dpg - lead free (rohs) pqfp 44: w78e058dfg - lead free (rohs) lqfp 48: w78e058dlg
w78e516d/w78e058d data sheet - 6 - 3 parts information list 3.1 lead free (rohs) parts information list table 3-1: lead free (rohs) parts information list part no. aprom flash size ldrom flash size ram package temperature grade W78E516DDG 512 bytes dip-40 pin w78e516dpg 512 bytes plcc-44 pin w78e516dfg 512 bytes pqfp-44 pin w78e516dlg 64k bytes 4k bytes 512 bytes lqfp-48 pin -40 o c~85 o c w78e058ddg 512 bytes dip-40 pin w78e058dpg 512 bytes plcc-44 pin w78e058dfg 512 bytes pqfp-44 pin w78e058dlg 32k bytes 4k bytes 512 bytes lqfp-48 pin -40 o c~85 o c
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 7 - revision a09 4 pin configurations 18 6 5 4 3 2 1 44 43 42 41 40 19 20 21 22 23 24 25 26 27 28 p1.3 p1.2 p1.4 t2ex, p1.1 t2, p1.0 ad0, p0.0 int3, p4.2 ad1, p0.1 ad2, p0.2 ad3, p0.3 vdd xtal2 xtal1 vss p2.1, a9 p4.0 p2.2, a10 p2.3, a11 p2.4, a12 p2.0, a8 p3.7, rd p3.6, wr dip 40-pin
w78e516d/w78e058d data sheet - 8 - 8 12 37 7 10 9 11 44 43 42 41 40 39 38 36 35 34 32 33 30 31 28 29 26 27 24 25 23 13 14 15 16 17 18 19 20 21 22 p1.6 p1.5 rst p1.7 rxd, p3.0 txd, p3.1 t0, p3.4 t1, p3.5 p1.3 p1.2 p1.4 t2ex, p1.1 t2, p1.0 ad0, p0.0 ad1, p0.1 ad2, p0.2 ad3, p0.3 vdd ale p0.7, ad7 p4.1 p0.6, ad6 p0.5, ad5 p0.4, ad4 p2.5, a13 p2.6, a14 p2.7, a15 xtal2 xtal1 vss p2.1, a9 p4.0 p2.2, a10 p2.3, a11 p2.0, a8 pqfp 44-pin int0, p3.2 p3.7, rd int1, p3.3 psen ea p3.6, wr 2 1 4 3 5 6 int2, p4.3 int3, p4.2 2 44 1 4 3 6 5 8 7 10 9 11 48 42 41 40 39 38 37 32 33 30 31 28 29 26 27 25 13 14 15 16 18 19 20 21 22 p2.7, a15 psen ad0, p0.0 ale ea p4.1 p0.6, ad6 p0.5, ad5 p2.4, a12 p2.3, a11 p2.2, a10 p2.1, a9 xtal2 p3.7, rd p3.6, wr xtal1 int2, p4.3 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 p1.6 p1.7 rst ad2, p0.3 ad2, p0.2 ad1, p0.1 p1.3 p1.4 p1.5 p1.2 p2.0, a8 p4.0 vss 12 17 23 24 34 35 36 46 47 43 45 p2.6, a14 p2.5, a13 nc vdd int3, p4.2 t2, p1.0 t2ex, p1.1 p0.7, ad7 p0.4, ad4 p3.1 p3.0 nc nc nc lqfp 48-pin p2.4, a12
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 9 - revision a09 5 pin descriptions symbol type descriptions e a i external access enable: this pin forces the processor to execute the external rom. the rom address and data will not be present on the bus if the ea pin is high and the program counter is within the internal rom area. oth- erwise they will be present on the bus. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs ori- ginate from this pin. ale o h address latch enable: a le is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscilla- tor frequency. an ale pulse is omitted during external data memory accesses. rst i l reset: a high on this pin for two machine cycles while the oscillator is run- ning resets the device. xtal1 i crystal 1: this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 o crystal 2: this is the crystal oscillator out put. it is the inversion of xtal1. vss i ground: ground potential. vdd i power supply: supply voltage for operation. p0.0 ? p0.7 i/o d port 0: port 0 is an open-drain bi-directional i/o port . this port also pro- vides a multiplexed low order address/dat a bus during accesses to external memory. p1.0 ? p1.7 i/o h port 1 : port 1 is a bi-directional i/o port with internal pull-ups. the bits have alternate functions which are described below: t2(p1.0): timer/counter 2 external count input t2ex(p1.1): timer/counter 2 re load/capture/direction control p2.0 ? p2.7 i/o h port 2: port 2 is a bi-directional i/o port with internal pull-ups. this port also provides the upper address bits for accesses to external memory. p3.0 ? p3.7 i/o h port 3: port 3 is a bi-directional i/o port with internal pull-ups. all bits have alternate functions, which are described below: rxd(p3.0): serial port 0 input txd(p3.1): serial port 0 output int0 (p3.2) : external interrupt 0 int1 (p3.3) : external interrupt 1 t0(p3.4) : timer 0 external input t1(p3.5) : timer 1 external input wr (p3.6) : external data memory write strobe rd (p3.7) : external data memory read strobe p4.0 ? p4.3 i/o h port 4: another bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o port or external interrupt input sources ( int2 / int3 ). * note : type i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open drain
w78e516d/w78e058d data sheet - 10 - 6 block diagram figure 6- 1 w78e516d/w78e058d block diagram
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 11 - revision a09 7 functional description the w78e516d/w78e058d series architecture cons ists of a core controller surrounded by various registers, four general purpose i/o ports, one spec ial purpose programmable 4-bits i/o port, 512 bytes of ram, three timer/counters, a serial port. the processor supports 111 different op-codes and refer- ences both a 64k program address space and a 64 k data storage space. 7.1 on-chip flash eprom the w78e516d/w78e058d series includes one 64k/ 32k bytes of main flash eprom for applica- tion program (aprom) and one 4k bytes of flash eprom for loader program (ldrom) when op- erating the in-system programming feature. in normal operation, t he microcontroller will execute the code from the 64k/32k bytes of main flash eprom . by setting program registers, user can force microcontroller to switch to the programming mode which microcontroller will execute the code (loader program) from the 4k bytes of auxiliary flash eprom, and this loader program is going to update the contents of the 64k/32k bytes of main flash eprom. after reset, the microcontroller executes the new application program in the main flash eprom. this in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. in some appli- cations, the in-system programming feature make it possible that the end-user is able to easily update the system firmware by the t hem without opening the chassis. 7.2 i/o ports the w78e516d/w78e058d series has four 8-bit ports and one extra 4-bit port. port 0 can be used as an address/data bus when external program is ru nning or external memory/device is accessed by movc or movx instruction. in these cases, it has strong pull-ups and pull-downs, and does not need any external pull-ups. otherwise it can be used as a general i/o port with open-drain circuit. port 2 is used chiefly as the upper 8-bits of the address bus when port 0 is used as an address/data bus. it also has strong pull-ups and pull-downs when it serves as an address bus. port1 and 3 act as i/o ports with alternate functions. port 4 is only availabl e on plcc/qfp/lqfp package type. it serves as a general purpose i/o port as port 1 and port 3. anot her bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o port or external interrupt input sources ( int2 / int3 ). 7.3 serial i/o the w78e516d/w78e058d series have one serial port that is functionally similar to the serial port of the original 8032 family. however the serial port on the w78e516d/w78e058d series can operate in different modes in order to obtain timing similarity as well. 7.4 timers timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide con- trol functions for timers 0 and 1. the t2con regist er provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the 8051 cpu. timer 2 is a special feature of the w78e516d/w78e058d series: it is a 16-bit ti mer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 c an operate as either an external event counter or
w78e516d/w78e058d data sheet - 12 - as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating mod- es: capture, auto-reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. 7.4.1 clock the w78e516d/w78e058d series are designed to be used with either a crystal oscillator or an ex- ternal clock. internally, the clock is divided by two before it is used by default. this makes the w78e516d/w78e058d series relatively insensit ive to duty cycle variations in the clock. 7.5 interrupts the interrupt structure in the w78e516d/w78e058d series is slightly different from that of the stan- dard 8052. due to the presenc e of additional features and peripherals, the number of interrupt sources and vectors has been increased. the w78e516d/w78e 058d series provides 8 interrupt resources with two priority level, including four external inte rrupt sources, three timer interrupts, serial i/o inter- rupts. 7.6 data pointers the data pointer of w78e516d/w78e058d series is same as standard 8052 that have one 16-bit da- ta pointer (dptr). 7.7 architecture the w78e516d/w78e058d series are based on the standard 8052 device. it is built around an 8-bit alu that uses internal registers for temporary st orage and control of the peripheral devices. it can ex- ecute the standard 8052 instruction set. 7.7.1 alu the alu is the heart of the w78e516d/w78e058d seri es. it is responsible for the arithmetic and logi- cal functions. it is also used in decision making, in case of jump instructions, and is also used in calcu- lating jump addresses. the user cannot directly us e the alu, but the instruction decoder reads the op-code, decodes it, and sequences the data through t he alu and its associated registers to generate the required result. the alu mainly uses the acc wh ich is a special function register (sfr) on the chip. another sfr, namely b register is also us ed multiply and divide instructions. the alu generates several status signals which are stored in the program status word register (psw). 7.7.2 accumulator the accumulator (acc) is the primary register used in arithmetic, logical and data transfer operations in the w78e516d/w78e058d series. since the accumulator is directly accessible by the cpu, most of the high speed instructions make use of the acc as one argument. 7.7.3 b register this is an 8-bit register that is used as the se cond argument in the mul and div instructions. for all other instructions it can be used simply as a general purpose register. 7.7.4 program status word this is an 8-bit sfr that is used to store the status bits of the alu. it holds the carry flag, the auxiliary carry flag, general purpose flags, the register bank select, the overflow flag, and the parity flag.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 13 - revision a09 7.7.5 stack pointer the w78e516d/w78e058d series has an 8-bit stack pointer which points to the top of the stack. this stack resides in the scratch pad ram in t he w78e516d/w78e058d series. hence the size of the stack is limited by the size of this ram. 7.7.6 scratch-pad ram the w78e516d/w78e058d series has a 256 bytes on- chip scratch-pad ram. this can be used by the user for temporary storage during program executi on. a certain section of this ram is bit address- able, and can be directly addressed for this purpose. 7.7.7 aux-ram aux-ram 0h~255h is addressed indirectly as the sa me way to access external data memory with the movx instruction. the data memory region is from 0000h to 00ffh. memory map shows the mem- ory map for this product series. w78e516d/w78e058 d series can read/write 256 bytes aux ram by the movx instruction.
w78e516d/w78e058d data sheet - 14 - 8 memory organization the w78e516d/w78e058d series separate the memo ry into two separate sections, the program memory and the data memory. the program memory is used to store the instruction op-codes, while the data memory is used to store data or for memory mapped devices. indirect addressing ram direct & indirect addressing ram sfrs direct addressing only 00h 7fh 80h ffh 64k bytes external data memory 64k bytes on chip ap flash ffffh 0000h ffffh 0000h 256 byte on chip aux ram 00h ffh 4k byte on chip ld rom 0000h fffh figure 8- 1 memory map 8.1 program memory (on-chip flash) the program memory on the w78e516d/w78e058d seri es can be up to 64k/32k bytes long. all in- structions are fetched for execution from this memory area. the movc instruction can also access this memory region. 8.2 scratch-pad ram and register map as mentioned before the w78e516d/w78e058d seri es have separate program and data memory areas. there are also several special function registers (sfrs) which can be accessed by software. the sfrs can be accessed only by direct addres sing, while the on-chip ram can be accessed by either direct or indirect addressing. indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00h 7fh 80h ffh 256 bytes ram and sfr data memory space figure 8- 2 w78e516d/w78e058 d ram and sfr memory map
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 15 - revision a09 since the scratch-pad ram is only 256bytes it can be used only when data cont ents are small. there are several other special purpose areas within the scratch-pad ram. these are illustrated in next fig- ure. bank 0 bank 1 bank 2 bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct ram indirect ram 00h 07h 28h 08h 0fh 10h 17h 18h 1fh 20h 21h 22h 23h 24h 25h 26h 27h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 7fh 80h ffh figure 8- 3 scratch-pad ram
w78e516d/w78e058d data sheet - 16 - 8.2.1 working registers there are four sets of working r egisters, each consisting of eight 8-bit registers. these are termed as banks 0, 1, 2, and 3. individual re gisters within these banks can be di rectly accessed by separate in- structions. these individual registers are named as r0, r1, r2, r3, r4, r5, r6 and r7. however, at one time the w78e516d/w78e058d series can work with only one particular bank. the bank selec- tion is done by setting rs1-rs0 bits in the psw. t he r0 and r1 registers are used to store the ad- dress for indirect accessing. 8.2.2 bit addressable locations the scratch-pad ram area from location 20h to 2fh is byte as well as bit addressable. this means that a bit in this area can be individually addressed. in addition some of the sfrs are also bit ad- dressable. the instruction decoder is able to distingu ish a bit access from a byte access by the type of the instruction itself. in the sfr area, any existing sfr whose address ends in a 0 or 8 is bit address- able. 8.2.3 stack the scratch-pad ram can be used for the stack. this area is selected by the stack pointer (sp), which stores the address of the t op of the stack. whenever a jump, ca ll or interrupt is invoked the re- turn address is placed on the stack. there is no rest riction as to where the stack can begin in the ram. by default however, the stack pointer contains 07h at reset. the user can then change this to any value desired. the sp will point to the last us ed value. therefore, the sp will be incremented and then address saved onto the stack. conversely, while popping from the stack the contents will be read first, and then the sp is decreased. 8.2.4 aux-ram aux-ram 0h~255h is addressed indirectly as the sa me way to access external data memory with the movx instruction. address pointer are r0 and r1 of the selected register bank and dptr register. a access to external data memory locations higher than 255 will be performed with the movx instruction in the same way as in the 8051. the aux-ram is disabled after power-on reset. setting the bit 4 in chpcon register will enable the access to aux-ram.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 17 - revision a09 9 special function registers the w78e516d/w78e058d series uses special function registers (sfrs) to control and monitor peripherals and their modes. the sfrs reside in th e register locations 80-ffh and are accessed by direct addressing only. some of the sfrs are bit addr essable. this is very useful in cases where us- ers wish to modify a particular bit without changing the others. the sfrs that are bit addressable are those whose addresses end in 0 or 8. the w78e516d/w78e058d series contain all the sfrs present in the standard 8052. however some additional sfrs are added. in some cases the unused bits in the original 8052, have been given new functions . the list of the sfrs is as follows. w78e516d/w78e058d special function registers (sfrs) and reset values f8 ff f0 +b chpenr f7 e8 ef e0 +acc e7 d8 +p4 df d0 +psw d7 c8 +t2con rcap2l rcap2h tl2 th2 cf c0 +xicon p4cona p4conb sfral sfrah sfrfd sfrcn c7 b8 +ip chpcon bf b0 +p3 p43al p43ah b7 a8 +ie p42al p42ah p2econ af a0 +p2 a7 98 +scon sbuf 9f 90 +p1 p41al p41ah 97 88 +tcon tmod tl0 tl1 th0 th1 auxr wdtc 8f 80 +p0 sp dpl dph p40al p40ah p0upr pcon 87 figure 9-1: special function register location table note: 1.the sfrs marked with a plus sign(+) are both byte- and bit-addressable. 2. the text of sfr with bold type char acters are extension function registers.
w78e516d/w78e058d data sheet - 18 - special function registers: symbol definition address msb bit address, symbol lsb reset chpenr chip enable register f6h 1111 0110b b b register f0h (f7) (f6) (f5) (f4) (f3) (f2) (f1) (f0) 0000 0000b acc accumulator e0h (e7) (e6) (e5) (e4) (e3) (e2) (e1) (e0) 0000 0000b p4 port 4 d8h p43 p42 p41 p40 0000 1111b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 (d0) p 0000 0000b th2 t2 reg. high cdh 0000 0000b tl2 t2 reg. low cch 0000 0000b rcap2h t2 capture low cbh 0000 0000b rcap2l t2 capture high cah 0000 0000b t2con timer 2 control c8h (cf) tf2 (ce) exf2 (cd) rclk (cc) tclk (cb) exen2 (ca) tr2 (c9) c/t2 (c8) cp/rl2 0000 0000b sfrcn sfr for program control c7h 0000 0000b sfrfd sfr for program data c6h 0000 0000b sfrah port4 base address high register c5h 0000 0000b sfral port4 base address low register c4h 0000 0000b p4conb port 4 control b c3h p43fun1 p43fun0 p43cmp1 p43com0 p42fun1 p42fun0 p42cmp1 p42cmp2 0000 0000b p4cona port 4 control a c2h p41un1 p41fun0 p41cmp1 p41com0 p40fun1 p40fun0 p40cmp1 p40cmp2 0000 0000b xicon external interrupt control c0h px3 ex3 ie3 it3 px2 ex2 ie2 it2 0000 0000b chpcon chip control bfh swreset enauxra m fbootsl fprogen xxx0 0000b [1] ip interrupt priority b8h (bf) - (be) - (bd) pt2 (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 x000 0000b p43ah port 4.3 comparator high address b5h 0000 0000b p43al port 4.3 comparator low address b4h 0000 0000b p3 port 3 b0h (b7) rd (b6) wr (b5) t1 (b4) t0 (b3) int1 (b2) int0 (b1) txd (b0) rxd 1111 1111b p2econ port 2 expanded control aeh p43csinv p42csin v p41csin v p40csin v - - 0000 0000b p42ah port 4.2 comparator high address adh 0000 0000b p42al port 4.3 comparator low address ach 0000 0000b ie interrupt enable a8h (af) ea (ae) - (ad) et2 (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0000 0000b p2 port 2 a0h (a7) a15 (a6) a14 (a5) a13 (a4) a12 (a3) a11 (a2) a10 (a1) a9 (a0) a8 1111 1111b sbuf serial buffer 99h xxxx xxxxb scon serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 0000 0000b p41ah port 4.1 comparator high address 95h 0000 0000b p41al port 4.1 comparator low address 94h 0000 0000b p1 port 1 90h (97) (96) (95) (94) (93) (92) (91) t2ex (90) t2 1111 1111b wdtc watchdog control 8fh enw clrw widl - - ps2 ps1 ps0 0000 0000b auxr auxiliary 8eh ale_off 0000 0110b th1 timer high 1 8dh 0000 0000b th0 timer high 0 8ch 0000 0000b tl1 timer low 1 8bh 0000 0000b tl0 timer low 0 8ah 0000 0000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 0000 0000b
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 19 - revision a09 tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0000 0000b pcon power control 87h smod smod0 - por gf1 gf0 pd idl 00x1 0000b p0upr port 0 pull up option register 86h p0up 0000 0000b p40ah hi address comparator of p4.0 85h 0000 0000b p40al lo address comparator of p4.0 84h 0000 0000b dph data pointer high 83h 0000 0000b dpl data pointer low 82h 0000 0000b sp stack pointer 81h 0000 0111b p0 port 0 80h (87) (86) (85) (84) (83) (82) (81) (80) 1111 1111b [1]: when cpu in f04kboot mode (ref. p65), chpco n=1xx0 0000b, other mode the chpcon=0xx0 0000b 9.1 sfr detail bit descriptions port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemonic: p0 address: 80h bit name function 7-0 p0.[7:0] port 0 is an open-drain bi-directional i/o por t. this port also provides a multiplexed low order address/data bus during accesses to external memory. stack pointer bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemonic: sp address: 81h bit name function 7-0 sp.[7:0] the stack pointer stores the scratc h-pad ram address where the stack begins. in other words it always points to the top of the stack. data pointer low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemonic: dpl address: 82h bit name function 7-0 dpl.[7:0] this is the low byte of the standard 8052 16-bit data pointer. data pointer high bit: 7 6 5 4 3 2 1 0
w78e516d/w78e058d data sheet - 20 - dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemonic: dph address: 83h bit name function 7-0 dph.[7:0] this is the high byte of the standard 8052 16-bit data pointer. p4.0 base address low byte register bit: 7 6 5 4 3 2 1 0 p40al.7 p40al.6 p40a l.5 p40al.4 p40al.3 p40al.2 p40al.1 p40al.0 mnemonic: p40al address: 84h bit name function 7-0 p40al.[7:0] the base address register for comparator of p4.0. p40al contains the low- order byte of address. p4.0 base address high byte register bit: 7 6 5 4 3 2 1 0 p40ah.7 p40ah.6 p40a h.5 p40ah.4 p40ah.3 p 40ah.2 p40ah.1 p40ah.0 mnemonic:p40ah address: 85h bit name function 7-0 p40ah.[7:0] the base address register for co mparator of p4.0. p40ah contains the high- order byte of address. port 0 pull up option register bit: 7 6 5 4 3 2 1 0 - - - - - - - p0up mnemonic: p0upr address: 86h bit name function 0 p0up 0: port 0 pins are open-drain. 1: port 0 pins are internally pulled-up. port 0 is structurally the same as port 2. power control bit: 7 6 5 4 3 2 1 0 smod smod0 - - gf1 gf0 pd idl mnemonic: pcon address: 87h bit name function 7 smod 1: this bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. 6 smod 0 0: framing error detection disable. scon.7 (sm0/fe) bit is used as sm0 (stan- dard 8052 function). 1: framing error detection enable. scon.7 (sm0/fe) bit is used to reflect as
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 21 - revision a09 frame error (fe) status flag. 5 - reserved 4 por 0: cleared by software. 1: set automatically when a power-on reset has occurred. 3 gf1 general purpose user flags. 2 gf0 general purpose user flags. 1 pd 1: the cpu goes into the power down mode. in this mode, all the clocks are stopped and program execution is frozen. 0 idl 1: the cpu goes into the idle mode. in this mode, the clocks cpu clock stopped, so program execution is frozen. but the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating. timer control bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 mnemonic: tcon address: 88h bit name function 7 tf1 timer 1 overflow flag. this bit is se t when timer 1 overflows. it is cleared auto- matically when the program does a timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 run control. this bit is set or cleared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag. this bit is se t when timer 0 overflows. it is cleared auto- matically when the program does a timer 0 interrupt service routine. software can also set or clear this bit. 4 tr0 timer 0 run control. this bit is set or cleared by software to turn timer/counter on or off. 3 ie1 interrupt 1 edge detect flag: set by hardware when an edge/level is detected on 1int . this bit is cleared by hardware when t he service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 2 it1 interrupt 1 type control. set/cleared by software to specify falling edge/ low level triggered external inputs. 1 ie0 interrupt 0 edge detect flag. set by hardware when an edge/level is detected on 0int . this bit is cleared by hardware wh en the service routine is vectored to only if the interrupt was edge triggered. other wise it follows the inverse of the pin. 0 it0 interrupt 0 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. timer mode control bit: 7 6 5 4 3 2 1 0
w78e516d/w78e058d data sheet - 22 - gate tc / m1 m0 gate tc / m1 m0 timer1 timer0 mnemonic: tmod address: 89h bit name function 7 gate gating control: when this bit is set, timer/counter 1 is enabled only while the 1int pin is high and the tr1 control bit is set. when cleared, the 1int pin has no effect, and timer 1 is enabled whenever tr1 control bit is set. 6 tc/ timer or counter select: when clear, timer 1 is incremented by the internal clock. when set, the timer counts falling edges on the t1 pin. 5 m1 timer 1 mode select bit 1. see table below. 4 m0 timer 1 mode select bit 0. see table below. 3 gate gating control: when this bit is set, timer/counter 0 is enabled only while the 0 int pin is high and the tr0 control bit is set. when cleared, the int0 pin has no ef- fect, and timer 0 is enabled whenever tr0 control bit is set. 2 tc/ timer or counter select: when clear, timer 0 is incremented by the internal clock. when set, the timer counts falling edges on the t0 pin. 1 m1 timer 0 mode select bit 1. see table below. 0 m0 timer 0 mode select bit 0. see table below. m1, m0: mode select bits: m1 m0 mode 0 0 mode 0: 8-bit timer/counter tlx serves as 5-bit pre-scale. 0 1 mode 1: 16-bit timer/counter, no pre-scale. 1 0 mode 2: 8-bit timer/counter with auto-reload from thx. 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/count er controlled by the standard timer0 control bits. th0 is an 8-bit timer only controlled by timer1 control bits. (timer 1) timer/counter 1 is stopped. timer 0 lsb bit: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 mnemonic: tl0 address: 8ah bit name function 7-0 tl0.[7:0] timer 0 lsb. timer 1 lsb bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 23 - revision a09 mnemonic: tl1 address: 8bh bit name function 7-0 tl1.[7:0] timer 1 lsb. timer 0 msb bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 mnemonic: th0 address: 8ch bit name function 7-0 th0.[7:0] timer 0 msb. timer 1 msb bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 mnemonic: th1 address: 8dh bit name function 7-0 th1.[7:0] timer 1 msb. auxr bit: 7 6 5 4 3 2 1 0 - - - - - - - ale_off mnemonic: auxr address: 8eh bit name function 0 ale_off 1: disable ale output 0: enable ale output watchdog timer control register bit: 7 6 5 4 3 2 1 0 enw clrw widl - - ps2 ps1 ps0 mnemonic: wdtc address: 8fh bit name function 7 enw enable watch-dog if set. 6 clrw clear watch-dog timer and pre-scalar if set. this flag will be cleared automati- cally. 5 widl if this bit is set, watch-dog is enabled under idle mode. if cleared, watch-dog is
w78e516d/w78e058d data sheet - 24 - disabled under idle mode. default is cleared. 2-0 ps2-0 watch-dog pre-scalar timer select. pre-scalar is selected when set ps2 ? 0 as fol- lows: ps2 ps1 ps0 pre-scalar select 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemonic: p1 address: 90h bit name function 7-0 p1.[7:0] general purpose i/o port. most instructions will read the port pins in case of a port read access, however in case of read-modi fy-write instructions, the port latch is read. p4.1 base address low byte register bit: 7 6 5 4 3 2 1 0 p41al.7 p41al.6 p41a l.5 p41al.4 p41al.3 p41al.2 p41al.1 p41al.0 mnemonic: p41al address: 94h bit name function 7-0 p41al.[7:0] the base address register for comparator of p4.1. p41al contains the low- order byte of address. p4.1 base address high byte register bit: 7 6 5 4 3 2 1 0 p41ah.7 p41ah.6 p41a h.5 p41ah.4 p41ah.3 p 41ah.2 p41ah.1 p41ah.0 mnemonic: p41ah address: 95h bit name function 7-0 p41ah.[7:0] the base address register for co mparator of p4.1. p41ah contains the high- order byte of address.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 25 - revision a09 serial port control bit: 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri mnemonic: scon address: 98h bit name function 7 sm0/fe serial port mode select bit 0 or framing error flag: the smod0 bit in pcon sfr determines whether this bit acts as sm0 or as fe. the operation of sm0 is described below. when used as fe, this bi t will be set to indicate an invalid stop bit. this bit must be manually cleared in software to clear the fe condition. 6 sm1 serial port mode select bit 1. see table below. 5 sm2 multiprocessor communication mode enable. the function of this bit is dependent on the serial port mode. mode 0: no effect. mode 1: checking valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is ignored if the received stop bit is not logic 1. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9th bit. 1 = reception is ignored if the received 9th bit is not logic 1. 4 ren receive enable: 0: disable serial reception. 1: enable serial reception. 3 tb8 this is the 9th bit to be transmitted in modes 2 and 3. this bit is set and cleared by software as desired. 2 rb8 in modes 2 and 3 this is the received 9th data bit. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0 it has no function. 1 ti transmit interrupt flag: this flag is se t by hardware at the end of the 8th bit time in mode 0, or at the beginning of the st op bit in all other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. however the restrictions of sm2 apply to this bit. this bit can be cleared only by software. sm1, sm0: mode select bits: mode sm0 sm1 description length baud rate 0 0 0 synchronous 8 tclk divided by 4 or 12 1 0 1 asynchronous 10 variable 2 1 0 asynchronous 11 tclk divided by 32 or 64 3 1 1 asynchronous 11 variable
w78e516d/w78e058d data sheet - 26 - serial data buffer bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemonic: sbuf address: 99h bit name function 7~0 sbuf serial data on the serial port is read from or written to this location. it actually consists of two separate internal 8-bit re gisters. one is the receive resister, and the other is the transmit buffer. any read access gets data from the receive data buffer, while write access is to the transmit data buffer. port 2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 mnemonic: p2 address: a0h bit name function 7-0 p2.[7:0] port 2 is a bi-directional i/o port with inte rnal pull-ups. this port also provides the upper address bits for accesses to external memory. interrupt enable bit: 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 mnemonic: ie address: a8h bit name function 7 ea global enable. enable/disable all interrupts. 6 - reserved 5 et2 enable timer 2 interrupt. 4 es enable serial port 0 interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. p4.2 base address low byte register bit: 7 6 5 4 3 2 1 0 p42al.7 p42al.6 p42a l.5 p42al.4 p42al.3 p42al.2 p42al.1 p42al.0 mnemonic: p42al address: ach
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 27 - revision a09 bit name function 7-0 p42al.[7:0] the base address register for comparator of p4.2. p42al contains the low- order byte of address. p4.2 base address high byte register bit: 7 6 5 4 3 2 1 0 p42ah.7 p42ah.6 p42a h.5 p42ah.4 p42ah.3 p 42ah.2 p42ah.1 p42ah.0 mnemonic:p42ah address: adh bit name function 7-0 p42ah.[7:0] the base address register for co mparator of p4.2. p42ah contains the high- order byte of address. port 2 expanded control bit: 7 6 5 4 3 2 1 0 p43csin p42csin p41c sin p40csin - - - - mnemonic: p2econ address:aeh bit name function 7 p43csinv the active polarity of p4.3 when pin p4.3 is defined as read and/or write strobe signal. 1 : p4.3 is active high when pin p4.3 is defined as read and/or write strobe signal. 0 : p4.3 is active low when pin p4.3 is defined as read and/or write strobe signal. 6 p42csinv the similarity definition as p43sinv. 5 p41csinv the similarity definition as p43sinv. 4 p40csinv the similarity definition as p43sinv. port 3 bit: 7 6 5 4 3 2 1 0 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 mnemonic: p3 address: b0h p3.7-0: general purpose input/output port. most instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, the port latch is read. these alter- nate functions are described below: bit name function 7 p3.7 rd 6 p3.6 wr 5 p3.5 t1 4 p3.4 t0
w78e516d/w78e058d data sheet - 28 - 3 p3.3 int1 2 p3.2 int0 1 p3.1 tx 0 p3.0 rx p4.3 base address low byte register bit: 7 6 5 4 3 2 1 0 p43al.7 p43al.6 p43a l.5 p43al.4 p43al.3 p43al.2 p43al.1 p43al.0 mnemonic: p43al address: b4h bit name function 7-0 p43al.[7:0] the base address register for comparator of p4.3. p43al contains the low- order byte of address. p4.3 base address high byte register bit: 7 6 5 4 3 2 1 0 p43ah.7 p43ah.6 p43a h.5 p43ah.4 p43ah.3 p 43ah.2 p43ah.1 p43ah.0 mnemonic: p43ah address: b5h bit name function 7-0 p43ah.[7:0] the base address register for co mparator of p4.3. p43ah contains the high- order byte of address. interrupt priority bit: 7 6 5 4 3 2 1 0 - - pt2 ps pt1 px1 pt0 px0 mnemonic: ip address: b8h bit name function 5 pt2 1: to set interrupt priority of timer 2 is higher priority level. 4 ps 1: to set interrupt priority of se rial port 0 is higher priority level. 3 pt1 1: to set interrupt priority of timer 1 is higher priority level. 2 px1 1: to set interrupt priority of exter nal interrupt 1 is higher priority level. 1 pt0 1: to set interrupt priority of timer 0 is higher priority level. 0 px0 1: to set interrupt priority of exter nal interrupt 0 is higher priority level. chip control bit: 7 6 5 4 3 2 1 0 swreset - - enauxram 0 0 fbootsl fprgen
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 29 - revision a09 (f04kmode) (must set 0) (must set 0) mnemonic: chpcon address: bfh bit name function 7 swreset(f04kmode) when this bit is set to 1, and both fbootsl and fprogen are set to 1. it will enforce microcontroller reset to initial condition just like power on reset. this action w ill re-boot the mi crocontroller and start to normal operation. to read this bit can determine that the f04kboot mode is running. 4 enauxram 1: enable on-chip aux-ram. 0: disable the on-chip aux-ram 1 fbootsl the loader program location select. 0: the loader program locates at the 64k/32k byte flash memory bank. 1: the loader program locates at the 4kb flash memory bank. 0 fprogen flash eprom programming enable 1: enable. the microcontroller sw itches to the programming flash mode after entering the idle mode and waken up from interrupt. the microcontroller will execute the loader program while in on- chip programming mode. 0: disable. the on-chip flash memory is read-only. in-system pro- grammability is disabled. external interrupt control bit: 7 6 5 4 3 2 1 0 px3 ex3 ie3 it3 px2 ex2 ie2 it2 mnemonic: xicon address: c0h bit name function 7 px3 external interrupt 3 priority high if set 6 ex3 external interrupt 3 enable if set 5 ie3 if it3 = 1, ie3 is set/cleared automa tically by hardware when interrupt is de- tected/serviced 4 it3 external interrupt 3 is falling-edge/low- level triggered when this bit is set/cleared by software 3 px2 external interrupt 2 priority high if set 2 ex2 external interrupt 2 enable if set 1 ie2 if it2 = 1, ie2 is set/cleared automa tically by hardware when interrupt is de- tected/serviced 0 it2 external interrupt 2 is falling-edge/low- level triggered when this bit is set/cleared by software port 4 control a
w78e516d/w78e058d data sheet - 30 - bit: 7 6 5 4 3 2 1 0 p41fun1 p41fun0 p41cmp1 p41cmp0 p40fun1 p40fun0 p40cmp1 p40cmp0 mnemonic: p4cona address: c2h bit name function 7,6 p41fun1 p41fun0 00: mode 0. p4.1 is a general purpose i/o port which is the same as port1. 01: mode 1. p4.1is a read strobe signal for chip select purpose. the address range depends on the sfr p41ah, p41al, p41cmp1 and p41cmp0. 10: mode 2. p4.1 is a write strobe signal for chip select purpose. the address range depends on the sfr p41ah,p41al,p41cmp1 and p41cmp0. 11: mode 3. p4.1 is a read/write strobe signal for chip select purpose. the ad- dress range depends on the sfr p41a h, p41al, p41cmp1, and p41cmp0. 5,4 p41cmp1 p41cmp0 chip-select signals address comparison: 00: compare the full address (16 bits length) with the base address register p41ah, p41al. 01: compare the 15 high bits (a15-a1) of address bus with the base address register p41ah, p41al. 10: compare the 14 high bits (a15-a2) of address bus with the base address register p41ah, p41al. 11: compare the 8 high bits (a15-a8) of address bus with the base address reg- ister p41ah, p41al. 3,2 p40fun1 p40fun0 the p4.0 function control bits which are the similar definition as p40fun1, p40fun0. . 1,0 p40cmp1 p40cmp0 the p4.0 address comparator length control bits which are the similar definition as p40cmp, p40cmp0. port 4 control b bit: 7 6 5 4 3 2 1 0 p43fun1 p43fun0 p43cmp1 p43cmp0 p42fun1 p42fun0 p42cmp1 p42cmp0 mnemonic: p4conb address: c3h bit name function 7,6 p43fun1 p43fun0 the p4.3 function control bits which are the similar definition as p43fun1, p43fun0. . 5,4 p43cmp1 p43cmp0 the p4.3 address comparator length control bits which are the similar definition as p43cmp1,p43cmp0. 3,2 p42fun1 p42fun0 the p4.2 function control bits which are the similar definition as p42fun1, p42fun0. . 1,0 p42cmp1 p42cmp0 the p4.2 address comparator length control bits which are the similar definition as p42cmp1,p42cmp0. sfr program of address low bit: 7 6 5 4 3 2 1 0 sfral.7 sfral.6 sfral.5 sfral.4 sfral.3 sfral.2 sfral.1 sfral.0
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 31 - revision a09 mnemonic: sfral address: c4h bit name function 7-0 sfral.[7:0] the programming address of on-chip flash memory in programming mode. sfrfal contains the low- order byte of address. sfr program of address high bit: 7 6 5 4 3 2 1 0 sfrah.7 sfrah.6 sfra h.5 sfrah.4 sfrah.3 sf rah.2 sfrah.1 sfrah.0 mnemonic: sfrah address: c5h bit name function 7-0 sfrah.[7:0] the programming address of on-chip flash memory in programming mode. sfrfah contains the high-order byte of address. sfr program for data bit: 7 6 5 4 3 2 1 0 sfrfd.7 sfrfd.6 sfrf d.5 sfrfd.4 sfrf d.3 sfrfd.2 sf rfd.1 sfrfd.0 sfrfd address: c6h bit name function 7-0 sfrfd.[7:0] the programming data for on- chip flash memory in programming mode. sfr for program control bit: 7 6 5 4 3 2 1 0 - wfwin oen cen ctrl3 ctrl2 ctrl1 ctrl0 sfrcn address: c7h bit name function 6 wfwin on-chip flash eprom bank select for in-system programming. 0: 64k bytes flash eprom bank is selected as destination for re- programming. 1: 4k bytes flash eprom bank is selected as destination for re- programming. 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3-0 ctrl[3:0] ctrl[3:0]: the flash control signals mode ctrl<3:0> wfwin oen cen sfrah,sfral sfrfd erase aprom 0010 0 1 0 x x program aprom 0001 0 1 0 address in data in
w78e516d/w78e058d data sheet - 32 - read aprom 0000 0 0 0 address in data out timer 2 control bit: 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 ct /2 cp rl /2 mnemonic: t2con address: c8h bit name function 7 tf2 timer 2 overflow flag: this bit is se t when timer 2 overflows. it can be set only if rclk and tclk are both 0. it is clear ed only by software. software can also set or clear this bit. 6 exf2 timer 2 external flag: a negative transition on the t2ex pin (p1.1) or timer 2 overflow will cause this flag to set based on the cp rl /2 , exen2 bits. if set by a negative transition, this flag must be cleared by software. setting this bit in software or detection of a negative transition on t2ex pin will force a timer interrupt if enabled. 5 rclk receive clock flag: this bit determi nes the serial port 0 time-base when re- ceiving data in serial modes 1 or 3. if it is 0, then timer 1 overflow is used for baud rate generation, otherwise timer 2 over flow is used. setting this bit forces timer 2 in baud rate generator mode. 4 tclk transmit clock flag: this bit det ermines the serial port 0 time-base when transmitting data in modes 1 and 3. if it is set to 0, the timer 1 overflow is used to generate the baud rate clock otherwise timer 2 overflow is used. setting this bit forces timer 2 in baud rate generator mode. 3 exen2 timer 2 external enable. this bit enables the ca pture/reload function on the t2ex pin if timer 2 is not generating baud clocks for the serial port. if this bit is 0, then the t2ex pin will be ignor ed, otherwise a negative transition de- tected on the t2ex pin will result in capture or reload. 2 tr2 timer 2 run control. this bit enables/disables the operation of timer 2. clear- ing this bit will halt the timer 2 and preserve the current count in th2, tl2. 1 ct /2 counter/timer select. this bit determi nes whether timer 2 will function as a timer or a counter. independent of this bi t, the timer will run at 2 clocks per tick when used in baud rate generator mode. 0 cp rl /2 capture/reload select. this bit deter mines whether the capture or reload function will be used for timer 2. if either rclk or tclk is set, this bit will be ignored and the timer will function in an auto-reload mode following each over- flow. if the bit is 0 then auto-reload will occur when timer 2 overflows or a fal- ling edge is detected on t2ex pin if exen2 = 1. if this bit is 1, then timer 2 captures will occur when a falling edge is detected on t2ex pin if exen2 = 1. timer 2 capture lsb
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 33 - revision a09 bit: 7 6 5 4 3 2 1 0 rcap2l.7 rcap2l.6 rcap2l.5 rcap2l.4 rcap2l.3 rcap2l.2 rcap2l.1 rcap2l.0 mnemonic: rcap2l address: cah bit name function 7-0 rcap2l.[7:0] this register is used to capture the tl2 value when a timer 2 is configured in capture mode. rcap2l is also used as the lsb of a 16-bit reload value when timer 2 is configured in auto-reload mode. timer 2 capture msb bit: 7 6 5 4 3 2 1 0 rcap2h.7 rcap2h.6 rcap2h.5 rcap2h.4 rcap2h.3 rcap2h.2 rcap2h.1 rcap2h.0 mnemonic: rcap2h address: cbh bit name function 7-0 rcap2h.[7:0] this register is used to capture the th2 value when a timer 2 is configured in capture mode. rcap2h is also used as the msb of a 16-bit reload value when timer 2 is configured in auto-reload mode. timer 2 lsb bit: 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 mnemonic: tl2 address: cch bit name function 7-0 tl2.[7:0] timer 2 lsb timer 2 msb bit: 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 mnemonic: th2 address: cdh bit name function 7-0 th2.[7:0] timer 2 msb program status word program status word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h bit name function
w78e516d/w78e058d data sheet - 34 - 7 cy carry flag: set for an arithmetic operation which re sults in a carry being generated from the alu. it is also used as the accumulator for the bit operations. 6 ac auxiliary carry: set when the previous operation resulted in a carry from the high order nibble. 5 f0 user flag 0: the general purpose flag that can be set or cleared by the user. 4 rs1 register bank select bits: 3 rs0 register bank select bits: 2 ov overflow flag: set when a carry was generated from the seventh bit but not from the 8 th bit as a result of the previous operation, or vice-versa. 1 f1 user flag 1: the general purpose flag that can be set or cleared by the user by software. 0 p parity flag: set/cleared by hardware to indicate odd/ even number of 1?s in the accumulator. rs.1-0: register bank selection bits: rs1 rs0 register bank address 0 0 0 00-07h 0 1 1 08-0fh 1 0 2 10-17h 1 1 3 18-1fh port 4 bit: 7 6 5 4 3 2 1 0 - - - - p4.3 p4.2 p4.1 p4.0 mnemonic: p4 address: d8h port 4, sfr p4 at address d8h, is a 4-bit mult ipurpose programmable i/o port. each bit can be con- figured individually by software. the port 4 has four different operation mode: in mode 0, p4.0 ? p4.3 is a bi-directional i/o port which is sa me as port 1. p4.2 and p4.3 also serve as external interrupt int3 and int2 if enabled. in mode 1, p4.0 ? p4.3 are read data strobe signals which are synchronized with rd signal at specified addresses. these signals can be used as chip -select signals for external peripherals. in mode 2 , p4.0 ? p4.3 are write data strobe signals which are synchronized with wr signal at speci- fied addresses. these signals can be used as ch ip-select signals for external peripherals. in mode 3, p4.0 ? p4.3 are read data strobe signals which are synchronized with rd or wr signal at specified addresses. these signals can be used as chip-select signals for external peripherals. when port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the sfr p4xah, p4xa l, p4cona and p4conb. the registers p4xah and p4xal contain the 16-bit base address of p4.x . the registers p4cona and p4conb contain the control bits to configure the port 4 operation mode.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 35 - revision a09 here is an example to program the p4.0 as a wr ite strobe signal at the i/o port address 1234h ~1237h and positive polarity, and p4.1~p4.3 are used as general i/o ports. mov p40ah,#12h mov p40al,#34h ;define the base i/o address 1234h for p4.0 as an special function mov p4cona,#00001010b ;define the p4.0 as a write strobe signal pin and the comparator mov p4conb,#00h ;p4.1~p4.3 as general i/o port which are the same as port1 mov p2econ,#10h ;write the p40sinv =1 to inverse the p4.0 write strobe polarity ;default is negative. then any instruction movx @dptr,a (with dptr =1234h~1237h) will generate the positive polarity write strobe signal at pin p4.0 . a nd the instruction mov p4,#xx will output the bit3 to bit1 of data #xx to pin p4.3~ p4.1. address bus bit length selectable comparator register p4xal p4xah equal p4.x mux 4->1 p4 register p4.x read write data i/o rd_cs wr_cs rd/wr_cs p4xcmp0 p4xcmp1 p4xfun0 p4xfun1 p4xcsinv p4.x input data bus register pin comparator the port 4 structure diagram accumulator bit: 7 6 5 4 3 2 1 0
w78e516d/w78e058d data sheet - 36 - acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h bit name function 7-0 acc the a or acc register is the standard 8052 accumulator. b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemonic: b address: f0h bit name function 7-0 b the b register is the standard 8052 r egister that serves as a second accumulator. chip enable register bit: 7 6 5 4 3 2 1 0 chpenr. 7 chpenr. 6 chpenr. 5 chpenr. 4 chpenr. 3 chpenr. 2 chpenr. 1 chpenr. 0 mnemonic: chpenr address: f6h the chpcon is read only by default .you must writ e #87,#59h sequentially to this special register chpenr to enable the chpcon write attribute, and write other value to disable chpcon write at- tribute. this register protects from wr iting to the chpcon register carelessly.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 37 - revision a09 10 instruction the w78e516d/w78e058d series execute all the in structions of the standard 8052 family. the opera- tions of these instructions, as well as their effects on flag and status bits, are exactly the same. op-code hex code bytes w78e516d/w78e058d series clock cycles nop 00 1 12 add a, r0 28 1 12 add a, r1 29 1 12 add a, r2 2a 1 12 add a, r3 2b 1 12 add a, r4 2c 1 12 add a, r5 2d 1 12 add a, r6 2e 1 12 add a, r7 2f 1 12 add a, @r0 26 1 12 add a, @r1 27 1 12 add a, direct 25 2 12 add a, #data 24 2 12 addc a, r0 38 1 12 addc a, r1 39 1 12 addc a, r2 3a 1 12 addc a, r3 3b 1 12 addc a, r4 3c 1 12 addc a, r5 3d 1 12 addc a, r6 3e 1 12 addc a, r7 3f 1 12 addc a, @r0 36 1 12 addc a, @r1 37 1 12 addc a, direct 35 2 12 addc a, #data 34 2 12 subb a, r0 98 1 12 subb a, r1 99 1 12 subb a, r2 9a 1 12 subb a, r3 9b 1 12 subb a, r4 9c 1 12
w78e516d/w78e058d data sheet - 38 - op-code hex code bytes w78e516d/w78e058d series clock cycles subb a, r5 9d 1 12 subb a, r6 9e 1 12 subb a, r7 9f 1 12 subb a, @r0 96 1 12 subb a, @r1 97 1 12 subb a, direct 95 2 12 subb a, #data 94 2 12 inc a 04 1 12 inc r0 08 1 12 inc r1 09 1 12 inc r2 0a 1 12 inc r3 0b 1 12 inc r4 0c 1 12 inc r5 0d 1 12 inc r6 0e 1 12 inc r7 0f 1 12 inc @r0 06 1 12 inc @r1 07 1 12 inc direct 05 2 12 inc dptr a3 1 24 dec a 14 1 12 dec r0 18 1 12 dec r1 19 1 12 dec r2 1a 1 12 dec r3 1b 1 12 dec r4 1c 1 12 dec r5 1d 1 12 dec r6 1e 1 12 dec r7 1f 1 12 dec @r0 16 1 12 dec @r1 17 1 12 dec direct 15 2 12 mul ab a4 1 48 div ab 84 1 48
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 39 - revision a09 op-code hex code bytes w78e516d/w78e058d series clock cycles da a d4 1 12 anl a, r0 58 1 12 anl a, r1 59 1 12 anl a, r2 5a 1 12 anl a, r3 5b 1 12 anl a, r4 5c 1 12 anl a, r5 5d 1 12 anl a, r6 5e 1 12 anl a, r7 5f 1 12 anl a, @r0 56 1 12 anl a, @r1 57 1 12 anl a, direct 55 2 12 anl a, #data 54 2 12 anl direct, a 52 2 12 anl direct, #data 53 3 24 orl a, r0 48 1 12 orl a, r1 49 1 12 orl a, r2 4a 1 12 orl a, r3 4b 1 12 orl a, r4 4c 1 12 orl a, r5 4d 1 12 orl a, r6 4e 1 12 orl a, r7 4f 1 12 orl a, @r0 46 1 12 orl a, @r1 47 1 12 orl a, direct 45 2 12 orl a, #data 44 2 12 orl direct, a 42 2 12 orl direct, #data 43 3 24 xrl a, r0 68 1 12 xrl a, r1 69 1 12 xrl a, r2 6a 1 12 xrl a, r3 6b 1 12
w78e516d/w78e058d data sheet - 40 - op-code hex code bytes w78e516d/w78e058d series clock cycles xrl a, r4 6c 1 12 xrl a, r5 6d 1 12 xrl a, r6 6e 1 12 xrl a, r7 6f 1 12 xrl a, @r0 66 1 12 xrl a, @r1 67 1 12 xrl a, direct 65 2 12 xrl a, #data 64 2 12 xrl direct, a 62 2 12 xrl direct, #data 63 3 24 clr a e4 1 12 cpl a f4 1 12 rl a 23 1 12 rlc a 33 1 12 rr a 03 1 12 rrc a 13 1 12 swap a c4 1 12 mov a, r0 e8 1 12 mov a, r1 e9 1 12 mov a, r2 ea 1 12 mov a, r3 eb 1 12 mov a, r4 ec 1 12 mov a, r5 ed 1 12 mov a, r6 ee 1 12 mov a, r7 ef 1 12 mov a, @r0 e6 1 12 mov a, @r1 e7 1 12 mov a, direct e5 2 12 mov a, #data 74 2 12 mov r0, a f8 1 12 mov r1, a f9 1 12 mov r2, a fa 1 12 mov r3, a fb 1 12 mov r4, a fc 1 12
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 41 - revision a09 op-code hex code bytes w78e516d/w78e058d series clock cycles mov r5, a fd 1 12 mov r6, a fe 1 12 mov r7, a ff 1 12 mov r0, direct a8 2 24 mov r1, direct a9 2 24 mov r2, direct aa 2 24 mov r3, direct ab 2 24 mov r4, direct ac 2 24 mov r5, direct ad 2 24 mov r6, direct ae 2 24 mov r7, direct af 2 24 mov r0, #data 78 2 12 mov r1, #data 79 2 12 mov r2, #data 7a 2 12 mov r3, #data 7b 2 12 mov r4, #data 7c 2 12 mov r5, #data 7d 2 12 mov r6, #data 7e 2 12 mov r7, #data 7f 2 12 mov @r0, a f6 1 12 mov @r1, a f7 1 12 mov @r0, direct a6 2 24 mov @r1, direct a7 2 24 mov @r0, #data 76 2 12 mov @r1, #data 77 2 12 mov direct, a f5 2 12 mov direct, r0 88 2 24 mov direct, r1 89 2 24 mov direct, r2 8a 2 24 mov direct, r3 8b 2 24 mov direct, r4 8c 2 24 mov direct, r5 8d 2 24 mov direct, r6 8e 2 24
w78e516d/w78e058d data sheet - 42 - op-code hex code bytes w78e516d/w78e058d series clock cycles mov direct, r7 8f 2 24 mov direct, @r0 86 2 24 mov direct, @r1 87 2 24 mov direct, direct 85 3 24 mov direct, #data 75 3 24 mov dptr, #data 16 90 3 24 movc a, @a+dptr 93 1 24 movc a, @a+pc 83 1 24 movx a, @r0 e2 1 24 movx a, @r1 e3 1 24 movx a, @dptr e0 1 24 movx @r0, a f2 1 24 movx @r1, a f3 1 24 movx @dptr, a f0 1 24 push direct c0 2 24 pop direct d0 2 24 xch a, r0 c8 1 12 xch a, r1 c9 1 12 xch a, r2 ca 1 12 xch a, r3 cb 1 12 xch a, r4 cc 1 12 xch a, r5 cd 1 12 xch a, r6 ce 1 12 xch a, r7 cf 1 12 xch a, @r0 c6 1 12 xch a, @r1 c7 1 12 xchd a, @r0 d6 1 12 xchd a, @r1 d7 1 12 xch a, direct c5 2 24 clr c c3 1 12 clr bit c2 2 12 setb c d3 1 12 setb bit d2 2 12 cpl c b3 1 12
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 43 - revision a09 op-code hex code bytes w78e516d/w78e058d series clock cycles cpl bit b2 2 12 anl c, bit 82 2 24 anl c, /bit b0 2 24 orl c, bit 72 2 24 orl c, /bit a0 2 24 mov c, bit a2 2 12 mov bit, c 92 2 24 acall addr11 71, 91, b1, 11, 31, 51, d1, f1 2 24 lcall addr16 12 3 24 ret 22 1 24 reti 32 1 24 ajmp addr11 01, 21, 41, 61, 81, a1, c1, e1 2 24 ljmp addr16 02 3 24 jmp @a+dptr 73 1 24 sjmp rel 80 2 24 jz rel 60 2 24 jnz rel 70 2 24 jc rel 40 2 24 jnc rel 50 2 24 jb bit, rel 20 3 24 jnb bit, rel 30 3 24 jbc bit, rel 10 3 24 cjne a, direct, rel b5 3 24 cjne a, #data, rel b4 3 24 cjne @r0, #data, rel b6 3 24 cjne @r1, #data, rel b7 3 24 cjne r0, #data, rel b8 3 24 cjne r1, #data, rel b9 3 24 cjne r2, #data, rel ba 3 24 cjne r3, #data, rel bb 3 24 cjne r4, #data, rel bc 3 24 cjne r5, #data, rel bd 3 24
w78e516d/w78e058d data sheet - 44 - op-code hex code bytes w78e516d/w78e058d series clock cycles cjne r6, #data, rel be 3 24 cjne r7, #data, rel bf 3 24 djnz r0, rel d8 2 24 djnz r1, rel d9 2 24 djnz r5, rel dd 2 24 djnz r2, rel da 2 24 djnz r3, rel db 2 24 djnz r4, rel dc 2 24 djnz r6, rel de 2 24 djnz r7, rel df 2 24 djnz direct, rel d5 3 24 table 10-1: instruction set for w78e516d/w78e058d
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 45 - revision a09 11 instruction timing a machine cycle consists of a sequence of 6 states, numbered s1 through s6. each state time lasts for two oscillator periods. thus a machine cycle take s 12 oscillator periods or 1us if the oscillator fre- quency is 12mhz. each state is divided into a phase 1 half and a phas e 2 half. the fetch/execute sequences in states and phases for various kinds of instructions. normally two program fetches are generated during each machine cycle, even if the instruct ion being executed doesn?t requir e it. if the instruction being exe- cuted doesn?t need more code bytes, the cpu simply ignores the extra fetch, and the program coun- ter is not incremented. execution of a one-cycle instruction begins dur ing state 1 of the machine cycle, when the op-codes is latched into the instruction register. a second fetch occurs during s4 of the same machine cycle. execution is complete at the end of state 6 of this machine cycle. the movx instructions take two machine cycles to execute. no program fetch is generated during the second cycle of a movx instruction. this is the only time program fetches are skipped. the fetch/execute sequence for movx instructions. the fetch/execute sequences are the same whether the program memory is internal or external to the chip. execution times do not depend on whether the program memory is internal or external. the signals and timing involved in program fetches wh en the program memory is external. if program memory is external, then the progr am memory read strobe psen is normally activated twice per ma- chine cycle. if an access to external data memo ry occurs, two psens pulse are skipped, because the address and data bus are being used for the data memory access. note that a data memory bus cy- cle takes twice as much time as a program memory bus cycle.
w78e516d/w78e058d data sheet - 46 - 12 power management the w78e516d/w78e058d has several features that help the user to control the power consumption of the device. the power saved features have basically the po wer down mode and the idle mode of operation. 12.1 idle mode the user can put the device into idle mode by writing 1 to the bit pcon.0. the instruction that sets the idle bit is the last instruction t hat will be executed before the device goes into idle mode. in the idle mode, the clock to the cpu is halt ed, but not to the interrupt, timer, watchdog timer and serial port blocks. this forces the cpu state to be frozen; the program counter, the stack pointer, the program status word, the accumulator and the other register s hold their contents. the port pins hold the logi- cal states they had at the time idle was activated. the idle mode can be terminated in two ways. since the interrupt controller is still acti ve, the activation of any enabled inte rrupt can wake up the processor. this will automatically clear the idle bit, terminate the idle mode, and the interrupt service routine (isr) will be executed. after the isr, execution of the program will continue from the instruction which put the device into idle mode. the idle mode can also be exited by activating the reset. the device can put into reset either by apply- ing a high on the external rst pin, a power on reset condition or a watchdog timer reset. the exter- nal reset pin has to be held high for at least two machine cycles i.e. 24 clock periods to be recognized as a valid reset. in the reset condition the progra m counter is reset to 0000h and all the sfrs are set to the reset condition. since the clock is already ru nning there is no delay and execution starts imme- diately. 12.2 power down mode the device can be put into power down mode by writ ing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed before the device goes into power down mode. in the power down mode, all the clocks are stopped and the device comes to a halt. all activity is completely stopped and the power consumption is reduced to the lowest possible value. the port pins output the values held by their respective sfrs. the w78e516d/w78e058d will exit the power down mode with a reset or by an external interrupt pin enabled as level detects. an external reset can be us ed to exit the power down state. the high on rst pin terminates the power down mode, and restar ts the clock. the program execution will restart from 0000h. in the power down mode, the clock is stopped, so the watchdog timer cannot be used to provide the reset to exit power down mode. the w78e516d/w78e058d can be woken from the power down mode by forcing an external inter- rupt pin activated, provided the corresponding in terrupt is enabled, while the global enable(ea) bit is set and the external input has been set to a level detect mode. if these conditions are met, then the high level on the external pin re-starts the oscillator. then device executes the interrupt service routine for the corresponding external interrupt. after the inte rrupt service routine is completed, the program execution returns to the instruction after one whic h put the device into power down mode and contin- ues from there.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 47 - revision a09 13 reset conditions the user has several hardware related options for placing the w78e516d/w78e058d into reset con- dition. in general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state depends on the source of reset. the user can use these flags to deter- mine the cause of reset using software. 13.1 sources of reset 13.1.1 external reset the device continuously samples t he rst pin at state s5p2 of every machine cycle. therefore the rst pin must be held for at least 2 machine cycles (24 clock cycles) to ensure detection of a valid rst high. the reset circuitry then synchronously applies the internal reset signal. thus the reset is a synchronous operation and requires the clock to be running to cause an external reset. for more tim- ing descript, please reference the character 21.4.5 (page 79). once the device is in reset condition, it will remain so as long as rst is 1. even after rst is deacti- vated, the device will continue to be in reset state for up to two machine cycles, and then begin pro- gram execution from 0000h. there is no flag as sociated with the external reset condition. 13.1.2 watchdog timer reset the watchdog timer is a free running timer with prog rammable time-out intervals. the user can clear the watchdog timer at any time, causing it to rest art the count. when the time-out interval is reached an interrupt flag is set. if the watc hdog reset is enabled and the watchdog timer is not cleared, the watchdog timer will generate a reset. this places the device into the reset condition. the reset condi- tion is maintained by hardware for two machine cycl es. once the reset is removed the device will be- gin execution from 0000h. 13.1.3 software reset the w78e516d/w78e058d offers a software reset to switch back to the ap flash eprom. setting chpcon bits 0, 1 and 7 to logic-1 creates a software reset to reset the cpu. 13.1.4 reset state most of the sfrs and registers on t he device will go to the same condition in the reset state. the pro- gram counter is forced to 0000h and is held there as long as the reset condition is applied. however, the reset state does not affect the on-chip ram. the data in the ra m will be preserved during the re- set. however, the stack pointer is reset to 07h, and therefore the stack contents will be lost. the ram contents will be lost if the vdd falls below approxima tely 2v, as this is the minimum voltage level re- quired for the ram to operate normally. therefore afte r a first time power on reset the ram contents will be indeterminate. during a power fail condition, if the power falls below 2v, the ram contents are lost. after a reset most sfrs are cleared. interrupts and timers are disabled. the watchdog timer is dis- abled if the reset source was a por. the port sfrs have 0ffh written into them which puts the port pins in a high state.
w78e516d/w78e058d data sheet - 48 - interrupts the w78e516d/w78e058d has a 2 priority level interr upt structure with 8 interrupt sources. each of the interrupt sources has an individual priority bit, fl ag, interrupt vector and enable bit. in addition, the interrupts can be globally enabled or disabled. 13.2 interrupt sources the external interrupts int0 and int1 can be either edge triggered or level triggered, depending on bits it0 and it1. the bits ie0 and ie1 in the tcon register are the flags which are checked to gener- ate the interrupt. in the edge triggered mode, the in tx inputs are sampled in every machine cycle. if the sample is high in one cycle and low in the nex t, then a high to low transition is detected and the interrupts request flag iex in tcon is set. the flag bit requests the interrupt. since the external inter- rupts are sampled every machine cy cle, they have to be held high or low for at least one complete machine cycle. the iex flag is automatically cleared when the service routine is called. if the level trig- gered mode is selected, then the reque sting source has to hold the pin lo w till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service r outine. if the interrupt contin- ues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same s ource. note that the external interrupts int2 and int3 . by default, the individual interrupt flag corresponding to external interrupt 2 to 3 must be cleared manually by software. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the over- flow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. the timer 2 interrupt is generated by a logical or of the tf2 and the exf2 flags. these flags are set by overflow or capture/reload events in the timer 2 operation. the hardware does not clear these flags when a timer 2 in terrupt is executed. software has to resolve the cause of the interrupt between tf2 a nd exf2 and clear the appropriate flag. the serial block can generate interrupts on receptio n or transmission. there are two interrupt sources from the serial block, which are obtained by the ri and ti bits in the scon sfr. these bits are not automatically cleared by the hardw are, and the user will have to cl ear these bits using software. all the bits that generate interrupts can be set or re set by hardware, and thereby software initiated in- terrupts can be generated. each of the individual in terrupts can be enabled or disabled by setting or clearing a bit in the ie sfr. ie also has a global enable/disable bit ea, which can be cleared to dis- able all the interrupts, at once. source vector address source vector address external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h timer 2 overflow 002bh external interrupt 2 0033h external interrupt 3 003bh table 13- 1 w78e516d/w78e058d interrupt vector table 13.3 priority level structure there are two priority levels for t he interrupts high, low. the interrupt sources can be individually set to either high or low levels. naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. however there exists a pre-defined hierar chy amongst the interrupts themselves. this hier- archy comes into play when the interrupt controlle r has to resolve simultaneous requests having the same priority level. this hierarchy is defined as shown on table.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 49 - revision a09 the interrupt flags are sampled every machine cycle. in the same machine cycle, the sampled inter- rupts are polled and their priority is resolved. if certain conditions are met then the hardware will exe- cute an internally generated lcall instruction which will vector the process to the appropriate inter- rupt vector address. the conditi ons for generating the lcall are; 1. an interrupt of equal or higher prio rity is not current ly being serviced. 2. the current polling cycle is the last machine cycle of the instruction currently being executed. 3. the current instruction does not involve a writ e to ie, ip, xicon registers and is not a reti. if any of these conditions are not met, then the lc all will not be generated. the polling cycle is re- peated every machine cycle, with the interrupts sampled in the same machine cycle. if an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interrupts are not remembered; every poll- ing cycle is new. the processor responds to a valid interrupt by ex ecuting an lcall instruction to the appropriate ser- vice routine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts, the tf0 or tf1 flags are cleared by hardware whene ver the processor vectors to the appropriate timer service routine. in case of external interrupt, /in t0 and /int1, the flags are cleared only if they are edge triggered. in case of serial interrupts, the flags are not cleared by hardwar e. in the case of timer 2 interrupt, the flags are not cleared by hardware. the hardware lcall behaves exactly like the soft- ware lcall instruction. this instruction saves t he program counter contents onto the stack, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lcall. these address of vector for the different sources are as shown on below table. the vector table is not evenly spaced; this is to accommodate future expansions to the device family. execution continues from the vect ored address till an reti instructi on is executed. on execution of the reti instruction the pr ocessor pops the stack and loads the pc with the contents at the top of the stack. the user must take care t hat the status of the st ack is restored to what is was after the hard- ware lcall, if the execution is to return to the interrupted program. the processor does not notice anything if the stack contents are modified and will proceed with execution from the address put back into pc. note that a ret instruction would perform exactly the same process as a reti instruction, but it would not inform the interr upt controller that the interrupt service routine is completed, and would leave the controller still thinking that the service r outine is underway. each interrupt source can be individually enabled or di sabled by setting or clearing a bit in registers ie. the ie register also contains a global disable bit, ea, which disables all interrupts at once. each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing bits in the ip registers. an inte rrupt service routine in progress ca n be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. so , if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are receiv ed simultaneously, an internal polling sequence deter- mines which request is serviced. this is called the ar bitration ranking. note that the arbitration ranking is only used to resolve simultaneous req uests of the same priority level.
w78e516d/w78e058d data sheet - 50 - table below summarizes the interrupt sources, flag bi ts, vector addresses, enable bits, priority bits, arbitration ranking, and external interrupt may wake up the cpu from power down mode. source flag vector address enable bit flag cleared by arbitration ranking power- down wakeup external interrupt 0 ie0 0003h ex0 (ie.0) hardware, software 1(highest) yes timer 0 overflow tf0 000bh et0 (ie.1) hardware, software 2 no external interrupt 1 ie1 0013h ex1 (ie.2) hardware, software 3 yes timer 1 overflow tf1 001bh et1 (ie.3) hardware, software 4 no serial port ri + ti 0023h es (ie.4) software 5 no timer 2 over- flow/match tf2 002bh et2 (ie.5) software 6 no external interrupt 2 xicon 0033h ex2 (xicon.2) hardware, software 7 yes external interrupt 3 xicon 003bh ex3 (xicon.6) hardware, software 8(lowest) yes table 13- 2 summary of interrupt sources 13.4 interrupt response time the response time for each interrupt source depends on several factors, such as the nature of the in- terrupt and the instruction underway. in the case of external interrupts int0 and int1 , they are sam- pled at s5p2 of every machine cycle and then their corresponding interrupt flags iex will be set or re- set. the timer 0 and 1 overflow flags are set at c3 of the machine cycle in which overflow has oc- curred. these flag values are polled only in the next machine cycle. if a request is active and all three conditions are met, then the hardware generated lcall is executed. this lcall itself takes four ma- chine cycles to be completed. thus there is a minimum time of five machine cycles between the inter- rupt flag being set and the interrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a higher or equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the service routine currently being executed. if the polling cycle is not the last mach ine cycle of the instruc- tion being executed, then an additional delay is intr oduced. the maximum response time (if no other interrupt is in service) occurs if the device is pe rforming a write to ie, ip and then executes a mul or div instruction. 13.5 interrupt inputs since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 6 cpu clocks to ensure proper sampling. if the external interrupt is high for at least
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 51 - revision a09 one machine cycle, and then hold it low for at least one machine cycle. this is to ensure that the tran- sition is seen and that interrupt request flag ien is set. ien is automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the ex ternal source must hold the request active until the requested interrupt is actually generated. if the exte rnal interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated. it is not necessary to clear the inter- rupt flag ien when the interrupt is level sens itive, it simply tracks the input pin level. if an external interrupt is enabled when the w78e516d/w78e058d is put into power down or idle mode, the interrupt will cause the processor to wa ke up and resume operation. refer to the section on power reduction modes for details.
w78e516d/w78e058d data sheet - 52 - 14 programmable timers/counters the w78e516d/w78e058d series have three 16-bit programmable timer/counters, a machine cycle equals 12 or 6 oscillator periods, and it depends on 12t mode or 6t mode that the user configured this device. 14.1 timer/counters 0 & 1 w78e516d/w78e058d has two 16-bit timer/counters. each of these timer/counters has two 8 bit registers which form the 16 bit counting register. fo r timer/counter 0 they are th0, the upper 8 bits register, and tl0, the lower 8 bit register. similarl y timer/counter 1 has two 8 bit registers, th1 and tl1. the two can be configured to operate either as timers, counting machine cycles or as counters counting external inputs. when configured as a "timer", the timer counts clock cycles. the timer clock can be programmed to be thought of as 1/12 of the system clock. in t he "counter" mode, the register is incremented on the falling edge of the external input pin, t0 in case of timer 0, and t1 for timer 1. the t0 and t1 inputs are sampled in every machine cycle at c4. if the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incre- mented. since it takes two machine cycles to rec ognize a negative transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. in either the "timer" or "counter" mode, the count register will be updated at c3. therefore, in the "timer" mode, the recog- nized negative transition on pin t0 and t1 can caus e the count register value to be updated only in the machine cycle following the one in which the negative edge was detected. the "timer" or "counter" function is selected by the " tc/ " bit in the tmod special function register. each timer/counter has one selection bit for its own; bit 2 of tmod selects the function for ti- mer/counter 0 and bit 6 of tmod selects the func tion for timer/counter 1. in addition each ti- mer/counter can be set to operate in any one of fo ur possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. 14.2 time-base selection w78e516d/w78e058d provides users with two modes of operation for the timer. the timers can be programmed to operate like the standard 8051 family, c ounting at the rate of 1/12 of the clock speed. this will ensure that timing loops on w78e516d/w78e058d and the standard 8051 can be matched. this is the default mode of operati on of the w78e516d/w78e058d timers. 14.2.1 mode 0 in mode 0, the timer/counter is a 13-bit counter. the 13-bit counter consists of thx (8 msb) and the five lower bits of tlx (5 lsb). the upper three bits of tlx are ignored. the timer/counter is enabled when trx is set and either gate is 0 or intx is 1. when tc / is 0, the timer/counter counts clock cycles; when tc / is 1, it counts falling edges on t0 (timer 0) or t1 (timer 1). for clock cycles, the time base be 1/12 speed, and the falling edge of the clock increments the counter. when the 13-bit value moves from 1fffh to 0000h, the timer overflow flag tfx is set, and an interrupt occurs if en- abled. this is illustrated in next figure below. 14.2.2 mode 1 mode 1 is similar to mode 0 except that the counting register forms a 16-bit counter, rather than a 13- bit counter. this means that all the bits of thx and tlx are used. roll-over occurs when the timer moves from a count of 0ffffh to 0000h. the timer over flow flag tfx of the relevant timer is set and if
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 53 - revision a09 enabled an interrupt will occur. the selection of the ti me-base in the timer mode is similar to that in mode 0. the gate function operates similarly to that in mode 0. 1/12 fosc t0=p3.4 (t1=p3.5) 0 1 tr0=tcon.4 (tr1=tcon.6) gate=tmod.3 (gate=tmod.7) int0 =p3.2 (int1 =p3.3) c/t =tmod.2 (c/t =tmod.6) 07 07 tfx interrupt tl0 (tl1) th0 (th1) tf0 (tf1) 4 m1, m0=tmod.1, tmod.0 (m1, m0=tmod.5, tmod.4) 00 01 figure 14- 1 timer/counters 0 & 1 in mode 0,1 14.2.3 mode 2 in mode 2, the timer/counter is in the auto reload mode. in this mode, tlx acts as an 8-bit count reg- ister, while thx holds the reload value. when the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tlx is reloaded with the conten ts of thx, and the counti ng process continues from here. the reload operation leaves t he contents of the thx register unchanged. counting is enabled by the trx bit and proper setting of gate and intx . as in the other two modes 0 and 1 mode 2 allows counting of clock/12 or pulses on pin tn. 1/12 fosc t0=p3.4 (t1=p3.5) 0 1 tr0=tcon.4 (tr1=tcon.6) gate=tmod.3 (gate=tmod.7) int0 =p3.2 (int1 =p3.3) c/t =tmod.2 (c/t =tmod.6) 07 07 tfx interrupt tl0 (tl1) th0 (th1) tf0 (tf1) timer/counter mode2 figure 14- 2 timer/counter 0 & 1 in mode 2
w78e516d/w78e058d data sheet - 54 - 14.2.4 mode 3 mode 3 has different operating methods for the two timer/counters. for timer/counter 1, mode 3 simply freezes the counter. timer/counter 0, however, conf igures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is shown in the figure. tl0 uses the timer/counter 0 control bits tc/ , gate, tr0, int0 and tf0. the tl0 can be used to count clock cycles (clock/12) or 1-to-0 transitions on pin t0 as determined by c/t (tmod.2). th0 is forced as a clock cycle counter (clock/12) and takes over the use of tr1 and tf1 from timer/counter 1. mode 3 is used in cases where an extra 8 bit timer is needed. with timer 0 in mode 3, timer 1 can still be used in modes 0, 1 and 2, but its flexibility is somewhat limited. while it s basic functionality is maintained, it no longer has control over its overflow flag tf1 and the enable bit tr1. timer 1 can still be used as a timer/counter and retains the use of gate and int1 pin. in this condition it can be turned on and off by switching it out of and into its own mode 3. it can also be used as a baud rate generator for the serial port. 1/12 fosc t0=p3.4 0 1 tr0=tcon.4 gate=tmod.3 int0 =p3.2 c/t =tmod.2 07 07 tf0 interrupt tl0 th0 tr1=tcon.6 tf1 interrupt figure 14-3 timer/counter mode 3 14.3 timer/counter 2 timer/counter 2 is a 16 bit counter . timer/counter 2 is equipped with a capture/reload capability. as with the timer 0 and timer 1 counters, there exists considerable flexibility in selecting and controlling the clock, and in defining the operating mode. the clock source for timer/counter 2 may be selected for either the external t2 pin (c/t2 = 1) or the cr ystal oscillator, which is divided by 12 (c/t2 = 0). the clock is then enabled when tr2 is a 1, and disabled when tr2 is a 0. 14.3.1 capture mode the capture mode is enabled by setting the cp rl /2 bit in the t2con register to a 1. in the capture mode, timer/counter 2 serves as a 16 bit up counte r. when the counter rolls over from 0ffffh to 0000h, the tf2 bit is set, which will generate an inte rrupt request. if the exen2 bit is set, then a nega- tive transition of t2ex pin will cause the value in the tl2 and th2 register to be captured by the rcap2l and rcap2h register s. this action also causes the exf2 bit in t2con to be set, which will
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 55 - revision a09 also generate an interrupt. (rclk,tclk, rl2cp / )= (0,0,1) 1/12 fosc t2=p1.0 0 1 t2ex=p1.1 c/t2 =t2con.1 exf2 timer2 interrupt t2con.6 tr2=t2con.2 exen2=t2con.3 tl2 th2 rcap2l rcap2h tf2 t2con.7 figure 14-4 16-bit capture mode 14.3.2 auto-reload mode, counting up the auto-reload mode as an up counter is enabled by clearing the cp rl /2 bit in the t2con regis- ter. in this mode, timer/counter 2 is a 16 bit up co unter. when the counter rolls over from 0ffffh, a reload is generated that causes the contents of the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers. the reload action also sets the tf2 bit. if the exen2 bit is set, then a negative transition of t2ex pin will also cause a reload. this action also sets the exf2 bit in t2con. (rclk,tclk, rl2cp / )= (0,0,0) 1/12 fosc t2=p1.0 0 1 c/t2 =t2con.1 exf2 timer2 interrupt t2con.6 tr2=t2con.2 tl2 th2 rcap2l rcap2h tf2 t2con.7 figure 14- 5 16-bit auto-reload mode, counting up
w78e516d/w78e058d data sheet - 56 - 14.3.3 baud rate generator mode the baud rate generator mode is enabled by setting ei ther the rclk or tclk bits in t2con register. while in the baud rate generator mode, timer/counter 2 is a 16 bit counter with auto reload when the count rolls over from 0ffffh. however, rolling over does not set the tf2 bit. if exen2 bit is set, then a negative transition of the t2ex pin will set exf2 bit in the t2con register and cause an interrupt request. rclk+tclk=1, rl2cp / =0 fosc t2=p1.0 0 1 t2ex=p1.1 c/t2 =t2con.1 exf2 timer2 interrupt t2con.6 tr2=t2con.2 exen2=t2con.3 tl2 th2 rcap2l rcap2h 1/16 1/16 1 1 0 0 rclk= t2con.5 tclk= t2con.4 1/2 01 timer1 overflow sm od= pcon.7 rx clock tx clock timer2 overflow 1/2 figure 14- 6 baud rate generator mode
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 57 - revision a09 15 watchdog timer the watchdog timer is a free-running timer which ca n be programmed by the user to serve as a sys- tem monitor, a time-base generator or an event timer. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time-out interval. when the time-out occurs a system reset can also be caused if it is enabled. the main use of the watchdog timer is as a system monitor. this is important in real-time control applications. in case of power glitches or electro- magnetic interference, the processor may begin to execute errant code. if th is is left unchecked the entire system may crash. the watchd og time-out selection will result in different time-out values de- pending on the clock speed. the watchdog timer will de disabled on reset. in general, software should restart the watchdog timer to put it into a known st ate. the control bits that support the watchdog ti- mer are discussed below. enw : enable watchdog if set. clrw : clear watchdog timer an d pre-scalar if set. this fl ag will be cleared automatically widl : if this bit is set, watch-dog is enabled under idle mode. if cleared, watchdog is disabled un- der idle mode. default is cleared. ps2, ps1, ps0: watchdog pre-sc alar timer select. pre-scalar is selected when set ps2 ? 0 as follows: ps2 ps1 ps0 pre-scalar select 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 the time-out period is obtained using the following equation: ms scalare osc 121000 pr2 1 14 ? (12t mode) before watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to wdtc.6 (clrw). after 1 is written to this bit, the 14-bit timer, pre-scalar and this bit will be reset on the next instruction cycle. the watchdog timer is cleared on reset.
w78e516d/w78e058d data sheet - 58 - osc 1/6 1/12 pre-scalar 14- bit timer clear clrw external reset internal reset wi dl idle enw figure 15- 1 watchdog timer block diagram typical watch-dog time-out period when osc = 20 mhz ps2 ps1 ps0 watchdog time-out period 0 0 0 19.66 ms 0 0 1 39.32 ms 0 1 0 78.64 ms 0 1 1 157.28 ms 1 0 0 314.57 ms 1 0 1 629.14 ms 1 1 0 1.25 s 1 1 1 2.50 s table 15- 1 watch-dog time-out period
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 59 - revision a09 16 serial port serial port in this device is a full duplex port. the serial port is capable of synchronous as well as asynchronous communication. in synchronous mode the device generates the clock and operates in a half duplex mode. in the asynchronous mode, full duplex operation is available. this means that it can simultaneously transmit and receive data. the tr ansmit register and the receive buffer are both ad- dressed as sbuf special function register. however any write to sbuf will be to the transmit regis- ter, while a read from sbuf will be from the receiver buffer register. the serial port can operate in four different modes as described below. 16.1 mode 0 this mode provides synchronous communication with external devices. in this mode serial data is transmitted and received on the rxd line. txd is used to transmit the shift clock. the txd clock is provided by the device whether it is transmitting or receiving. this mode is therefore a half duplex mode of serial communication. in this mode, 8 bits are transmitted or received per frame. the lsb is transmitted/received first. the baud rate is fixed at 1/ 12 of the oscillator frequency. this baud rate is determined by the sm2 bit (scon.5). when this bit is set to 0, then the serial port runs at 1/12 of the clock. this additional facility of programmable baud rate in mode 0 is the only difference between the standard 8051 and w78e516d/w78e058d. the functional block diagram is shown below. data enters and leaves the serial port on the rxd line. the txd line is used to output the shift clock. the shift clock is used to shift data into and out of this device and the device at the other end of the line. any instruction that causes a write to sbuf will start the transmission. the shift clock w ill be activated and data will be shi fted out on the rxd pin till all 8 bits are transmitted. if sm2 = 1, then the data on rxd will appear 1 clock period before the falling edge of shift clock on txd. the clock on txd then re mains low for 2 clock periods, and then goes high again. if sm2 = 0, the data on rxd will appear 3 cloc k periods before the falling edge of shift clock on txd. the clock on txd then remains low for 6 cloc k periods, and then goes high again. this ensures that at the receiving end the data on rxd line can ei ther be clocked on the rising edge of the shift clock on txd or latched when the txd clock is low.
w78e516d/w78e058d data sheet - 60 - 1/12 fosc 0 tx clock rx clock ti ri tx shift tx start rx shift load sbuf shift clock ri ren sm2 clock sin parout sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt rxd txd rxd p3.0 alternate input function p3.0 alternate output function p3.1 alternate output function 1/4 1 receive shift register figure 16- 1 serial port mode 0 the ti flag is set high in s6p2 following the end of tr ansmission of the last bit. the serial port will re- ceive data when ren is 1 and ri is zero. the shift clock (txd) will be activated and the serial port will latch data on the rising edge of shift clock. the external device should therefore present data on the falling edge on the shift clock. this process continues till all the 8 bits have been receiv ed. the ri flag is set in s6p2 following the last rising edge of the sh ift clock on txd. this will stop reception, till the ri is cleared by software. 16.2 mode 1 in mode 1, the full duplex asynchronous mode is used. serial communication frames are made up of 10 bits transmitted on txd and received on rxd. the 10 bi ts consist of a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive mode, the stop bit goes into rb8 in the sfr scon. the baud rate in this mode is variable. the serial baud can be programmed to be 1/16 or 1/32 of the timer 1 over- flow. since the timer 1 can be set to different reload values, a wide variation in baud rates is possible. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at s6p2 follow- ing the first roll-over of divide by 16 counter. the ne xt bit is placed on txd pin at s6p2 following the next rollover of the divide by 16 counter. thus the transmission is synchronized to the divide by 16 counters and not directly to the write to sbuf signal. after all 8 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the s6p2 state after the stop bit has been put out on txd pin. this will be at the 10th rollover of the di vide by 16 counters after a write to sbuf. reception is enabled only if ren is high. the serial por t actually starts the re ceiving of serial data, with the detection of a falling edge on the rxd pin. t he 1-to-0 detector continuously monitors the rxd line, sampling it at the rate of 16 times the se lected baud rate. when a falling edge is detected, the divide by 16 counters is immediately reset. this help s to align the bit boundaries with the rollovers of the divide by 16 counters.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 61 - revision a09 the 16 states of the counter effect ively divide the bit time into 16 slices. the bit detection is done on a best of three basie. the bit detector samples the rxd pin, at the 8th, 9th an d 10th counter states. by using a majority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejec- tion feature of the serial port. if the first bit detect ed after the falling edge of rxd pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of t he bits are also detected and shifted into the sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 1/2 1/16 tx clock rx clock ti ri tx shift tx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 timer 1 overflow 1 receive shift register 01 01 tclk rclk timer 2 overflow figure 16- 2 serial port mode 1 16.3 mode 2 this mode uses a total of 11 bits in asynchrono us full-duplex communication. the functional descrip- tion is shown in the figure below. the frame consists of one start bit (0), 8 data bits (lsb first), a pro-
w78e516d/w78e058d data sheet - 62 - grammable 9th bit (tb8) and a stop bit (1). the 9th bit received is put into rb8. the baud rate is pro- grammable to 1/32 or 1/64 of the oscillator frequen cy, which is determined by the smod bit in pcon sfr. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at s6p2 following the first roll-over of the divide by 16 count er. the next bit is placed on txd pin at s6p2 fol- lowing the next rollover of the divide by 16 counter. thus the transmission is synchronized to the di- vide by 16 counters, and not directly to the write to sbuf signal. after all 9 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the s6p2 state after the stop bit has been put out on txd pin. this will be at the 11th rollover of the di vide by 16 counters after a write to sbuf. reception is enabled only if ren is high. the serial port actual ly starts the receiving of serial data, with the de- tection of a falling edge on the rxd pin. the 1-to-0 de tector continuously monitors the rxd line, sam- pling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the divide by 16 counters is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counters. the 16 states of the co unter effectively divide the bit time into 16 slices. the bit detection is done on a best of three basis. the bit detector samples the rxd pin, at the 8th, 9th and 10th coun- ter states. by using a majority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejection feature of the serial port. 1/2 1/16 tx clock rx clock ti ri tx shift tx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 fosc/2 1 d8 tb8 receive shift register figure 16- 3 serial port mode 2 if the first bit detected after the falling edge of rxd pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of the bits are also detected and shifted into the sbuf. af- ter shifting in 9 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 63 - revision a09 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. mode 3 this mode is similar to mode 2 in all respects, ex cept that the baud rate is programmable. the user must first initialize the serial related sfr scon before any communication can take place. this in- volves selection of the mode and baud rate. the ti mer 1 should also be initialized if modes 1 and 3 are used. in all four modes, transmission is starte d by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by t he condition ri = 0 and ren = 1. this will generate a clock on the txd pin and shift in 8 bits on the rxd pi n. reception is initiated in the other modes by the incoming start bit if ren = 1. the external device will start the comm unication by transmitting the start bit. tx clock rx clock ti ri tx shift tx start rx shift load sbuf clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb8 start stop 0 1 bit detector 1-to-0 detector d8 tb8 receive shift register 1/2 1/16 smod sample 1/16 0 timer 1 overflow 1 01 01 tclk rclk timer 2 overflow figure 15- 4 serial port mode 3 sm0 sm1 mode type baud clock frame size start bit stop bit 9th bit function 0 0 0 synch. 4 or 12 tclks 8 bits no no none 0 1 1 asynch. timer 1 or 2 10 bits 1 1 none
w78e516d/w78e058d data sheet - 64 - 1 0 2 asynch. 32 or 64 tclks 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 or 2 11 bits 1 1 0, 1 table 16- 1 serial ports modes
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 65 - revision a09 17 f04kboot mode (boot from 4k bytes of ldrom ) the w78e516d/w78e058d boots from aprom program memory(64k/32k bytes) by default at power on reset or reset-pin reset. on some occasions, user can force the w78e516d/w78e058d booting from the ldrom program memory (4k bytes) at power on reset or external re set. the settings for this special mode as follow. f04kboot mode p4.3 p2.7 p2.6 mode x l l fo4kboot l x x fo4kboot p2.7 p2.6 rst 300ms hi-z the reset timing for entering f04kboot mode 10ms hi-z p4.3 rst the reset tim ing for entering f04kboot m ode hi-z 300 m s 10 m s note1: the possible situation that you need to enter f04kboot mode is when the aprom program can not run normally and w78e516d/w78e058d can not jump to ldrom to execute on chip pro-
w78e516d/w78e058d data sheet - 66 - gramming function. then you can use this f04kboot mode to force the w78e516d/w78e058d jump to ldrom and run on chip programming proc edure. when you design your system, you can connect the pins p26, p27 to switches or jumper s. for example in a cd rom system, you can con- nect the p26 and p27 to play and eject buttons on the panel. when the aprom program is fail to execute the normal application program. user c an press both two buttons at the same time and then switch on the power of the personal computer to force the w78e516d/w78e058d to enter the f04kboot mode. after power on of personal computer, you can release both play and eject but- ton. note2: in application system design, user must take care the p2, p3, ale, /ea and /psen pin value at reset to avoid w78e516d/w78e058d entering the programming mode or f04kboot mode in normal operation.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 67 - revision a09 18 isp(in-system programming) isp is the ability of programmable mcu to be pr ogrammed while f/w code in ap-rom or ld-rom (isp work voltage 3.3-5.5v). the w78e058d/516d equips one 32k byte of main rom bank for application program (called aprom) and one 4k byte of auxiliary rom bank for loader program (called ldrom). in the normal operation, the microcontroller exec utes the code in the aprom. if the content of aprom needs to be modified, the w78e058d/516d allows user to ac tivate the in-system programming (isp) mode by setting the chpcon register. the chpcon is read-only by default, software must write two spe- cific values 87h, then 59h sequentially to the chpenr register to enable the chpcon write attribute. writing chpenr register with the values except 87h and 59h will close chpcon reg- ister write attribute. the w78e058d/516d achieves all in-system programming operations including enter/exit isp mode, program, eras e, read ... etc, during device in the idle mode. setting the bit chpcon.0 the device will enter in-system programm ing mode after a wake-up from idle mode. be- cause device needs proper time to complete the isp operations before awaken from idle mode, soft- ware may use timer interrupt to control the duratio n for device wake-up from idle mode. to perform isp operation for revising contents of aprom, so ftware located at aprom setting the chpcon reg- ister then enter idle mode, after awaken from idle mode the device executes the corresponding inter- rupt service routine in ldrom. because the device will clear the program counter while switching from aprom to ldrom, the first execution of reti in struction in interrupt serv ice routine will jump to 00h at ldrom area. the device offers a software reset for switching back to aprom while the con- tent of aprom has been updated completely. setting chpcon register bit 0, 1 and 7 to logic-1 will result a software reset to reset the cpu . the software reset serves as a external reset. this in- system programming feature makes the job easy and efficient in which the application needs to up- date firmware frequently. in some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. sfrah, sfral: the objective address of on-chip rom in the in-system programming mode. sfrah contains the high-order byte of address, sfral contains the low-order byte of address. sfrfd: the programming data for on-chip rom in programming mode. sfrcn: the control byte of on-chip rom programming mode. sfrcn (c7) bit name function 7 - reserve. 6 wfwin on-chip rom bank select for in-system programming. 0: 32k/64k bytes rom bank is se lected as destination for re- programming. 1: 4k bytes rom bank is selected as destination for re-programming. 5 oen rom output enable. 4 cen rom chip enable. 3, 2, 1, 0 ctrl [3:0] the flash control signals
w78e516d/w78e058d data sheet - 68 - mode wfwin oen cen ctrl <3:0> sfrah, sfral sfrfd erase 32kb/64kb aprom 0 1 0 0010 x x program 32kb/64kb aprom 0 1 0 0001 address in data in read 32kb/64kb aprom 0 0 0 0000 address in data out erase 4kb ldrom 1 1 0 0010 x x program 4kb ldrom 1 1 0 0001 address in data in read 4kb ldrom 1 0 0 0000 address in data out
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 69 - revision a09 start the algorithm of in-system programming enter in-system programming mode ? (conditions depend on user's application) setting control registers mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h setting tim er (about 1.5us) and enable tim er interrupt start tim er and enter idle m ode. ( cpu will be wakened from idle mode by tim er interrupt, then enter in-system programming mode) execute the normal application program no yes end cpu will be wakened by interrupt and re- boot from 4kb ldrom to execute the loader program. go part 1:aprom procedure of entering in-system programming mode
w78e516d/w78e058d data sheet - 70 - part 2: 4kb ldrom procedure of updating the aprom go timer interrupt service routine: stop timer & disable interrupt is f04kboot mode? (chpcon.7=1) reset the chpcon register: mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h n o yes setting timer and enable timer interrupt for wake-up . (15ms for erasing operation) setting erase operation mode: mov sfrcn,#22h (erase 64kb aprom) start timer and enter idle mode. (erasing...) end of erase operation. cpu will be wakened by timer interrupt. pgm pgm setting timer and enable timer interrupt for wake-up . (150us for program operation) end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces. setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h software reset cpu and re-boot from the 64kb aprom. mov chpenr,#87h mov chpenr,#59h mov chpcon,#83h end executing new code from address 00h in the 64kb aprom. yes no note: setting the chpcon from 00h to 03h will clear the program counter (pc). 19 config bits during the on-chip flash eprom operation mode, the flash eprom can be programmed and veri- fied repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom and thos e operations on it are described below. the w78e516d/w78e058d has several special setting registers, including the security register and company/device id registers, which can not be accessed in programming mode. those bits of the security registers can not be changed once they have been programmed from high to low. they
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 71 - revision a09 can only be reset through erase-all operation. the contents of the company id and device id regis- ters have been set in factory. b0 b1 config bits b2b3 b4 b5 b6 b7 b0 : lock bit logic 0 : enable, all of the aprom /ldrom/config b its w ill be locked . b1 : movc inhibit logic 0 : the movc instruction in external memory cannot access the code in internal memory logic 1 : no restriction . b5 : machine cycle select logic 0 : 6t logic 1 : 12t b 7 : o scillator c ontrol logic 0 : 1/2 gain logic 1 : f ull gain default 1 for all security bits. reserved bits must be kept in logic 1. bit 0: lock bits this bit is used to protect the customer's program code in the w78e516d/w78e058d. it may be set after the programmer finishes the programming and veri fies sequence. once these bits are set to logic 0, both the flash data and special setting registers can not be accessed again. bit 1: movc inhibit this bit is used to restrict the accessible region of the movc instruction. it can prevent the movc in- struction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a mo vc instruction in internal program memory space will always be able to access the rom data in both internal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. bit 5: machine cycle select this bit is select mcu core, default value is logic 1( 12t). once these bits are set to logic 0, the mcu core is 6t. bit 7: crystal select if this bit is set to logic 0 (24 mhz), the emi effect w ill be reduce. if this bit is set to logic 1 (40 mhz ), the w78e516d/w78e058d could to use 40mhz crystal, but the emi effect is major. so we provide the option bit which could be chose by customer.
w78e516d/w78e058d data sheet - 72 - 20 typical application circuits external program memory and crystal a9 a11 psen a1 vcc ad2 rst a8 r a3 a13 a12 c2 64kb rom 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 11 12 13 15 16 17 18 19 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ce oe o0 o1 o2 o3 o4 o5 o6 o7 ad5 ad5 ad4 c1 ad7 ad3 a10 ad1 74373 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1 11 d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 oc g ad2 a15 a14 ad1 a7 ale a4 crystal a11 vcc ad5 a6 a2 a0 ad6 ad4 a12 W78E516DDG-40dip 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 20 40 ea xta l1 xta l2 rst p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd/p3.7 wr/p3.6 psen ale txd / p3. 1 rxd/p3.0 vss vdd a8 a5 a1 a6 or w78e058ddg-40dip a4 10uf a0 ad7 a2 ad2 ad3 a15 a14 a3 a10 ad7 a9 ad6 ad1 ad0 a5 a13 ad4 ad6 ad3 ad0 8.2k a7 ad0 figure a expanded external data memory and oscillator 64kb ram 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 13 14 15 17 18 19 20 21 22 30 24 29 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 cs1 cs2 oe we ad7 a13 a10 ad4 a12 a7 8.2k a15 a13 ad2 a5 a6 10uf a1 ad5 a8 a3 a2 ale ad6 ad1 a12 a15 a4 a8 a5 vcc rst ad0 a10 ad1 a4 ad1 ad6 /wr vcc ad7 a14 ad6 74373 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1 11 d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 oc g or w78e058ddg-40dip a14 vcc ad5 a6 ad2 ad4 a7 a2 ad4 /rd ad5 a9 ad7 ad3 a0 a11 a9 a1 oscillator a0 ad3 vcc ad0 a11 ad3 ad2 a3 ad0 W78E516DDG-40dip 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 20 40 ea xta l 1 xta l 2 rst p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd/p3.7 wr/p3.6 psen ale txd / p3. 1 rxd/p3.0 vss vdd figure b
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 73 - revision a09 21 electrical characteristics 21.1 absolute maximum ratings symbol parameter min max unit dc power supply v dd ? v ss 2.4 5.5 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t a -40 +85 c note: exposure to conditions beyond those listed un der absolute maximum ratings may adversely af- fects the lift and reliability of the device.
w78e516d/w78e058d data sheet - 74 - 21.2 d.c. electrical characteristics t a =-40 ~+85 , v dd =2.4v~5.5v, v ss =0v sym parameter test condition min typ *1 max unit v il input low voltage (ports 0~4, /ea, xtal1, rst) 2.4 < v dd < 5.5v -0.5 0.2v dd - 0.1 v v ih input high voltage (ports 0~4, /ea) 2.4 < v dd < 5.5v 0.2v dd +0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 2.4 < v dd < 5.5v 0.7v dd v dd + 0.5 v v ol output low voltage (ports 0~4, ale, /psen) v dd =4.5v, i ol = 12.0ma *3,*4 v dd =2.4v, i ol = 8.0ma *3,*4 0.4 v v oh1 output high voltage (ports 1~4) v dd =4.5v, i oh = -300 a *4 v dd =2.4v, i oh = -20 a *4 2.4 2.0 v v oh2 output high voltage (ports 0 & 2 in exter- nal bus mode, ale, /psen) v dd =4.5v, i oh = -8.0ma *4 v dd =2.4v, i oh = -2.0ma *4 2.4 2.0 v i il logical 0 input cur- rent (ports 1~4) v dd =5.5v, v in =0.4v -45 -50 a i tl logical 1-to-0 tran- sition current (ports 1~4) v dd =5.5v, v in =2.0v *2 -510 -650 a i li input leakage cur- rent (port 0) 0 < v in < v dd +0.5 1.0 10 a active mode *5 @12mhz, v dd =5.0v @40mhz, v dd =5.0v @12mhz, v dd =3.3v @20mhz, v dd =3.3v 10.4 18.2 3.6 4.4 ma idle mode @12mhz, v dd =5.0v @40mhz, v dd =5.0v @12mhz, v dd =3.3v @20mhz, v dd =3.3v 3.4 10.3 1.3 1.9 ma i dd power supply cur- rent power-down mode <1 50 a
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 75 - revision a09 r rst rst-pin internal pull-down resistor 2.4 < v dd < 5.5v 30 350 k note: *1: typical values are not guaranteed. the values li sted are tested at room temperature and based on a limited number of samples. *2: pins of ports 1~4 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. *3: under steady state (non -transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 20ma maximum i ol per 8-bit port: 40ma maximum total i ol for all outputs: 100ma *4: if i oh exceeds the test condition, v oh will be lower than the listed specification. if i ol exceeds the test condition, v ol will be higher than the listed specification. *5: tested while cpu is kept in reset state and ea=h, port0=h. voltage max. frequency 6t/12t mode note 4.5-5.5v 40mhz 12t 4.5-5.5v 20mhz 6t 2.4v 20mhz 12t 2.4v 10mhz 6t frequency vs voltage table 21.3 ac characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the inter nal routing capacitance. most of the specifications can be expressed in terms of mu ltiple input clock periods (t cp ), and actual parts will usually experi- ence less than a 20 ns variation. the numbers below represent the performance expected from a 0.6 micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed fop 4 - 40 mhz 1
w78e516d/w78e058d data sheet - 76 - clock period tcp 25 - - ns 2 clock high tch 10 - - ns 3 clock low tcl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - - - ns 4 address hold from ale low t aah 1 t cp - - - ns 1, 4 ale low to psen low t apl 1 t cp - - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - 2 t cp - ns 4 psen pulse width t psw 3 t cp - 3 t cp - ns 4 notes: 1. p0.0 ? p0.7, p2.0 ? p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " " (due to buffer driving delay and wire loading) is 20 ns. data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - - 3 t cp+ ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " " (due to buffer driving delay and wire loading) is 20 ns. data write cycle item symbol min. typ. max. unit ale low to wr low t daw 3 t cp - - 3 t cp + ns data valid to wr low t dad 1 t cp - - - ns data hold from wr high t dwd 1 t cp - - - ns wr pulse width t dwr 6 t cp - 6 t cp - ns note: " " (due to buffer driving delay and wire loading) is 20 ns.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 77 - revision a09 port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 t cp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 t cp - - ns note: ports are read during s5p2, and output data becomes avail able at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. 21.4 timing waveforms 21.4.1 program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw
w78e516d/w78e058d data sheet - 78 - 21.4.2 data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar 21.4.3 data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 79 - revision a09 21.4.4 port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds 21.4.5 reset pin access cycle v ss v dd pof internal reset power 1 = reset state 0 = cpu free running ~0.7v reset pin ale crystal clock 65536 crystal clock ~2.0v 12 crystal clock = 1 machine cycle 24 crystal clock
w78e516d/w78e058d data sheet - 80 - 22 package dimensions 22.1 40-pin dip 1.37 1.22 0.054 0.048 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 2.055 2.070 52.20 52.58 015 0.090 2.29 0.650 0.630 16.00 16.51 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 81 - revision a09 22.2 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b eh e y a a 1 seating plane d g g e symbol min nom max max nom min dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
w78e516d/w78e058d data sheet - 82 - 22.3 44-pin pqfp 0.25 0.10 0.010 0.004 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.006 0.15 - - 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.510 0.025 0.063 0.004 0 10 0.394 0.520 0.031 0.398 0.530 0.037 9.9 0.80 12.95 0.65 1.60 10.00 13.20 0.8 10.1 13.45 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.20 12.95 10.1 10.00 9.9 10 0 0.10 .0315 0.01 0.02 0.25 0.5 seating plane 11 22 12 see detail f e b a y 1 a a 2 l l 1 c e e h 1 d 44 h d 34 33 detail f
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 83 - revision a09 22.4 48-pin lqfp
w78e516d/w78e058d data sheet - 84 - application note: in-system programming software examples this application note illustrates the in-system programmability of the mi crocontroller. in this example, microcontroller will boot from aprom bank and wa iting for a key to enter in-system programming mode for re-programming the contents of aprom. while entering in-system programming mode, mi- crocontroller executes the loader program in 4kb ldrom bank. the loader program erases the aprom then reads the new code data from external sram buffer (or through other interfaces) to up- date the aprom. example 1: ;******************************************************************************************************************* ;* example of aprom program: program will sc an the p1.0. if p1.0 = 0, enters in-system ;* programming mode for updating the contents of aprom code else executes the current rom code. ;* xtal = 40 mhz ;******************************************************************************************************************* .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 0h ljmp 100h ;jump to main program ;************************************************************************ ;* timer0 service vector org=000bh ;************************************************************************ org 00bh clr tr0 ;tr0=0,stop timer0 mov tl0,r6 mov th0,r7 reti ;************************************************************************ ;* aprom main program ;************************************************************************ org 100h main_: mov a,p1 ;scan p1.0 anl a,#01h cjne a,#01h,program_ ;if p1.0=0, enter in-system ;programming mode jmp normal_mode program_: mov chpenr,#87h ; chpenr=87h, chpcon ; register wrte enable mov chpenr,#59h ; chpenr=59h, chpcon ; register write enable mov chpcon,#03h ;chpcon=03h, enter in-system ; programming mode
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 85 - revision a09 mov tcon,#00h ;tr=0 timer0 stop mov ip,#00h ;ip=00h mov ie,#82h ;timer0 interrupt enable for ;wake-up from idle mode mov r6,#feh ;tl0=feh mov r7,#ffh ;th0=ffh mov tl0,r6 mov th0,r7 mov tmod,#01h ;tmod=01h,set timer0 a 16-bit timer mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode for launching ;the in-system programmability ;******************************************************************************** ;* normal mode aprom program: depending user's application ;******************************************************************************** normal_mode: . ;user's application program . . . . example 2: ;***************************************************************************************************************************** ;* example of 4kb ldrom program: this lorder program will erase the aprom first, then reads the new ;* code from external sram and program them into aprom bank. xtal = 40 mhz ;***************************************************************************************************************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 000h ljmp 100h ;jump to main program ;************************************************************************ ;* 1. timer0 service vector org=0bh ;************************************************************************ org 000bh clr tr0 ;tr0=0,stop timer0 mov tl0,r6 mov th0,r7 reti ;************************************************************************ ;* 4kb ldrom main program
w78e516d/w78e058d data sheet - 86 - ;************************************************************************ org 100h main_4k: mov chpenr,#8 7h ;chpenr=87h, chpcon write enable. mov chpenr,#59h ;chpenr=59h, chpcon write enable. mov 7fh,#01h ;set f04kboot mode flag. mov a,chpcon anl a,#01h cjne a,#00h,update_ ;check chpcon bit 0 mov 7fh,#00h ;flag=0, not in the f04kboot mode. mov chpcon,#01h ;chpcon=01h, enable in-system programming. mov chpenr,#00h ;disable chpcon write attribute mov tcon,#00h ;tcon=00h ,tr=0 timer0 stop mov tmod,#01h ;tmod=01h ,set timer0 a 16bit timer mov ip,#00h ;ip=00h mov ie,#82h ;ie=82h,timer0 interrupt enabled mov r6,#feh mov r7,#ffh mov tl0,r6 mov th0,r7 mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode update_: mov chpenr,#00h ;disable chpcon write-attribute mov tcon,#00h ;tcon=00h ,tr=0 tim0 stop mov ip,#00h ;ip=00h mov ie,#82h ;ie=82h,timer0 interrupt enabled mov tmod,#01h ;tmod=01h ,mode1 mov r6,#3ch ;set wake-up time for erase operation, ;about 15ms. depending on user's ;system clock rate. mov r7,#b0h mov tl0,r6 mov th0,r7 erase_p_4k: mov sfrcn,#22h ;sfrcn(c7h)=22h erase mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode( for erase operation) ;********************************************************************* ;* blank check ;********************************************************************* mov sfrcn,#0h ;read aprom mode mov sfrah,#0h ;start address = 0h mov sfral,#0h mov r6,#fbh ;set timer for read operation, about 1.5us. mov r7,#ffh
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 87 - revision a09 mov tl0,r6 mov th0,r7 blank_check_loop: setb tr0 ;enable timer 0 mov pcon,#01h ;enter idle mode mov a,sfrfd ;read one byte cjne a,#ffh,blank_check_error inc sfral ;next address mov a,sfral jnz blank_check_loop inc sfrah mov a,sfrah cjne a,#c0h,blank_check_loop ;end address=bfffh jmp program_rom blank_check_error: mov p1,#f0h mov p3,#f0h jmp $ ;******************************************************************************* ;* re-programming aprom bank ;******************************************************************************* program_rom: mov dptr,#0h ;the address of new rom code mov r2,#00h ;target low byte address mov r1,#00h ;target high byte address mov dptr,#0h ;external sram buffer address mov sfrah,r1 ;sfrah, target high address mov sfrcn,#21h ;sfrcn(c7h)=21 (program ) mov r6,#0ch ;set timer for programming, about 150us. mov r7,#feh mov tl0,r6 mov th0,r7 prog_d_: mov sfral,r2 ;sfral(c4h)= low byte address movx a,@dptr ;read data from external sram buffer mov sfrfd,a ;sfrfd(c6h)=data in mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode( prorgamming) inc dptr inc r2 cjne r2,#0h,prog_d_ inc r1 mov sfrah,r1 cjne r1,#c0h,prog_d_ ;***************************************************************************** ; * verify aprom bank ;***************************************************************************** mov r4,#03h ;error counter mov r6,#fbh ;set timer for read verify, about 1.5us. mov r7,#ffh
w78e516d/w78e058d data sheet - 88 - mov tl0,r6 mov th0,r7 mov dptr,#0h ;the start address of sample code mov r2,#0h ;target low byte address mov r1,#0h ;target high byte address mov sfrah,r1 ;sfrah, target high address mov sfrcn,#00h ;sfrcn=00 (read rom code) read_verify_: mov sfral,r2 ;sfral(c4h)= low address mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h inc r2 movx a,@dptr inc dptr cjne a,sfrfd,error_ cjne r2,#0h,read_verify_ inc r1 mov sfrah,r1 cjne r1,#c0h,read_verify_ ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov chpenr,#87h ;chpenr=87h mov chpenr,#59h ;chpenr=59h mov chpcon,#83h ;chpcon=83h, software reset. error_: djnz r4,update_ ;if error occurs, repeat 3 times. . ;in-system programming fail, user's ;process to deal with it.
w78e516d/w78e058d data sheet publication release date: feb 15, 2011 - 89 - revision a09 23 revision history version date page description a01 june 24, 2008 - initial issued a02 august 21,2008 7,8 update pin assignment. a03 september 1,2008 - update w78i516d/w78i058d parts a04 november 3,2008 update dc table typo error a05 january 7,2009 74 update v il and v ih . a06 april 2, 2009 - - - update dc table revise some typing errors rename sfr 86h por register to p0upr a07 april 22,2009 70 revise the application circuit a08 june 30,2009 6 65 70 71 1. revise the table 3-1 2. add the picture for ?f04kboot mode? of p4.3 3. revise the isp flow chart 4. revise the config bits 5. remove the ?preliminary? character each page a09 feb 15,2011 18 65 70 79 1. revise the default reset value for chpcon 2. add the reset-pin reset can entry the f04kboot mode. 3. revise the flow chart of isp programming 4. revise the config bits 5. add the external reset pin timing
w78e516d/w78e058d data sheet - 90 - important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dy- namic, brake or safety systems designed for vehicu lar use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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